1
2
15
16
17
SCLK
CS
Sample
N
Sample
N + 1
t
S
29
32
18
B15
B14
X
X
X
X
SDI
X
B1
B0
X
B2
33
34
43
44
45
48
X
X
X
X
X
X
SDO
3
Data from Sample N
ADC
3
SDO
2
,
DAISY
3
SDO
1
,
DAISY
2
{D11}
1
{D10}
1
{D1}
1
{D0}
1
{D11}
2
{D10}
2
{D1}
2
{D0}
2
{D11}
3
{D10}
3
{D1}
3
{D0}
3
{D11}
1
{D10}
1
{D1}
1
{D0}
1
{D11}
2
{D10}
2
{D1}
2
{D0}
2
{D11}
1
{D10}
1
{D1}
1
{D0}
1
Data from Sample N
ADC
2
Data from Sample N
ADC
1
27
28
50
59
60
61
64
49
X
X
X
X
X
X
CS
SDI
SCLK
DAISY
1
SDO
1
SDI
DGND
ADC
1
ADC
2
ADC
N
CS
SDO
SCLK
Host Controller
CS
SDI
SCLK
DAISY
2
SDO
2
CS
SDI
SCLK
DAISY
N
SDO
N
SBAS492 – JULY 2015
8.4.1.3.1
Daisy-Chain Topology
A typical connection diagram showing multiple devices in daisy-chain mode is shown in
. The CS,
SCLK, and SDI inputs of all devices are connected together and controlled by a single CS, SCLK, and SDO pin
of the host controller, respectively. The DAISY
1
input pin of the first ADC in the chain is connected to DGND, the
SDO
1
output pin is connected to the DAISY
2
input of ADC
2
, and so forth. The SDO
N
pin of the Nth ADC in the
chain is connected to the SDI pin of the host controller. The devices do not require any special hardware or
software configuration to enter daisy-chain mode.
Figure 92. Daisy-Chain Connection Schematic
A typical timing diagram for three devices connected in daisy-chain mode is shown in
Figure 93. Three Devices Connected in Daisy-Chain Mode Timing Diagram
At the falling edge of the CS signal, all devices sample the input signal at their respective selected channels and
enter into conversion phase. For the first 16 SCLK cycles, the internal register settings for the next conversion
can be entered using the SDI line that is common to all devices in the chain. During this time period, the SDO
outputs for all devices remain low. At the end of conversion, every ADC in the chain loads its own conversion
result into an internal 16-bit shift register. For the 12-bit device, the internal shift register is loaded with 12 bits of
output data followed by 0000 in the LSB. At the 16th SCLK falling edge, every ADC in the chain outputs the MSB
bit on its own SDO output pin. On every subsequent SCLK falling edge, the internal shift register of each ADC
latches the data available on its DAISY pin and shifts out the next bit of data on its SDO pin. Therefore, the
digital host receives the data of ADC
N
, followed by the data of ADC
N–1
, and so forth (in MSB-first fashion). In
total, a minimum of 16 × N SCLK falling edges are required to capture the outputs of all N devices in the chain.
This example uses three devices in a daisy-chain connection, so 3 × 16 = 48 SCLK cycles are required to
capture the outputs of all devices in the chain along with the 16 SCLK cycles to input the register settings for the
next conversion, resulting in a total of 64 SCLK cycles for the entire data frame. Note that the overall throughput
of the system is proportionally reduced with the number of devices connected in a daisy-chain configuration.
Copyright © 2015, Texas Instruments Incorporated
39
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