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SWRS037B – JANUARY 2006 – REVISED MARCH 2015

The last four bits (3:0) in the status byte con-tains FIFO_BYTES_AVAILABLE. This field contains the
number of bytes free for writing into the TX FIFO. When FIFO_BYTES_AVAILABLE=15, 15 or more bytes
are free.

Table 5-2

gives a status byte summary.

Table 5-2. Status Byte Summary

BITS

NAME

DESCRIPTION

Stays high until power and crystal have stabilized. Should always be low when using the

CHIP_RDYn

SPI interface.

Indicates the current main state machine mode.
The binary number is the value, the result is the state, and the definition is the current
main state machine mode.

000 = Idle : IDLE state

(1)

001 = Not used : Not used

6:04

STATE[2:0]

010 = TX : Transmit mode
011 = FSTXON : Fast TX ready
100 = CALIBRATE : Frequency synthesizer calibration is running
101 = SETTLING : PLL is settling
110 = Not used : Not used
111 = TXFIFO_UNDERFLOW : TX FIFO has underflowed. Acknowledge with SFTX

3:00

FIFO_BYTES_AVAILABLE[3:0]

The number of free bytes in the TX FIFO.

(1)

Also reported for some transitional states instead of SETTLING or CALIBRATE, due to a small error.

5.5.2

Register Access

The configuration registers on the CC1150 are located on SPI addresses from 0x00 to 0x2E.

Table 5-12

lists all configuration registers. The detailed description of each register is found in

Section 5.20

All configuration registers can be both written and read. The read/write bit controls if the register should be
written or read. When writing to registers, the status byte is sent on the SO pin each time a header byte or
data byte is transmitted on the SI pin. When reading from registers, the status byte is sent on the SO pin
each time a header byte is transmitted on the SI pin.

Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit in the
address header. The address sets the start address in an internal address counter. This counter is
incremented by one each new byte (every 8 clock pulses). The burst access is either a read or a write
access and must be terminated by setting CSn high.

For register addresses in the range 0x30 through 0x3D, the burst bit is used to select between status
registers (burst bit is 1) and command strobes (burst bit is 0). See more in

Section 5.5.3

. Because of this,

burst access is not available for status registers, so they must be read one at a time. The status registers
can only be read.

5.5.3

SPI Read

When reading register fields over the SPI interface while the register fields are updated by the radio
hardware (for example, MARCSTATE or TXBYTES), there is a small, but finite, probability that a single
read from the register is being corrupt. As an example, the probability of any single read from TXBYTES
being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to the

CC1150

Errata Notes

[8]

for more details.

5.5.4

Command Strobes

Command Strobes may be viewed as single byte instructions to CC1150. By addressing a Command
Strobe register, internal sequences will be started. These commands are used to disable the crystal
oscillator, enable transmit mode, flush the TX FIFO, and so on. The nine command strobes are listed in

Table 5-11

Detailed Description

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