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SLOS758G – DECEMBER 2011 – REVISED MARCH 2020
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Detailed Description
Copyright © 2011–2020, Texas Instruments Incorporated
lists the format of the direct command mode, and
shows an example.
Table 6-10. Direct Command Mode
Start
Cmd x
(Optional data or command)
Stop
Figure 6-9. Direct Command Example of Sending 0x0F (Reset) (Using SPI With SS Mode)
The other Direct Command Codes from MCU to TRF7963A are described in
6.12.2 FIFO Operation
The FIFO is a 12-byte register at address 0x1F with byte storage locations 0 to 11. FIFO data is loaded in
a cyclical manner and can be cleared by a reset command (0x0F, see
showing this Direct
Command).
Associated with the FIFO are two counters and three FIFO status flags. The first counter is a 4-bit FIFO
byte counter (bits B0 to B3 in register 0x1C) that keeps track of the number of bytes loaded into the FIFO.
If the number of bytes in the FIFO is n, the register value is n – 1 (number of bytes in FIFO register). If 8
bytes are in the FIFO, the FIFO counter (bits B0 to B3 in register 0x1C) has the value 7.
A second counter (12 bits wide) indicates the number of bytes being transmitted (registers 0x1D and
0x1E) in a data frame. An extension to the transmission-byte counter is a 4-bit broken-byte counter also
provided in register 0x1E (bits B0 to B3). Together these counters make up the TX length value that
determines when the reader generates the EOF byte.
FIFO status flags are as follows:
1.
FIFO overflow
(bit B4 of register 0x1C): Indicates that the FIFO was loaded too soon
2.
FIFO level too low
(bit B5 of register 0x1C): Indicates that only three bytes are left to be transmitted
(Can be used during transmission.)
3.
FIFO level high
(bit B6 of register 0x1C): Indicates that nine bytes are already loaded into the FIFO
(Can be used during reception to generate a FIFO reception IRQ. This is to notify the MCU to service
the reader in time to ensure a continuous data stream.)
