DNx-SL-514 Synchronous Serial Interface Board
Chapter 1
8
Introduction
May 2018
www.ueidaq.com
508.921.4600
© Copyright 2018
United Electronic Industries, Inc.
Figure 1-3 SSI Transmission Waveform
SSI data bit transfers occur using the following transmission sequence
(refer to
•
Clock and data are held high when devices are in an idle state.
•
When the master controller needs data, it starts outputting its clock
pulse train.
•
When the slave device is in idle and detects a low on the clock pin, it
shifts the MSB of the data word queued for transmission out its DataOut
pin on the rising edge of the clock, and subsequently each next data bit
transmits on the next rising edge of the master clock until the LSB shifts
out.
•
The master controller latches each incoming bit on the falling edge of its
clock.
•
When the full word is received by the master controller, the master holds
its clock high for the user-programmed pause time (t
p
).
•
When the full word is transmitted out of the slave device, the slave holds
its data low for a user-programmable transfer timeout period (t
m
), which
starts on the falling edge of the clock synchronized to the LSB of data.
•
After the t
m
period, the slave drives its DataOut pin high.
The master controller and slave device use the pause time (t
p
) duration to reset
their state machines to idle, and setup for the next word for transmission/
reception.
NOTE:
A master defect protocol error will occur if the slave device does not
drive its data output high at the end of the t
p
period or low between the
last rising edge of the clock (plus t
v
delay * 2) and end of t
m
period.
A slave defect protocol error will occur if the master clock is not high for
the full t
p
period (clock high is too short vs the programmed value).
CLK
Data
MSB
MSB-1
LSB
t
v
LSB+1
t
m
t
p
T
t
v
= data delay time
t
m
= transfer timeout (monoflop time)
T = 1/baud rate
t
p
= pause time
