AXI Bridge for PCI Express v2.4
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PG055 June 4, 2014
Chapter 4:
Design Flow Steps
Placement Constraints
The AXI Bridge for PCI Express core provides a Xilinx design constraint (XDC) file for all
supported PCIe, Part, and Package permutations. You can find the generated XDC file in the
Sources tab of the Vivado IDE after generating the IP in the Customize IP dialog box.
For design platforms, it might be necessary to manually place and constrain the underlying
blocks of the AXI Bridge for the PCIe core. The modules to assign a LOC constraint include:
• the embedded integrated block for PCIe itself
• the GTX transceivers (for each channel)
• the PCIe differential clock input (if utilized)
The following subsection describes example constraints for the 7 series architecture.
Constraints for Virtex-7 and Kintex-7 FPGAs
This section highlights the LOC constraints to be specified in the XDC file for the AXI Bridge
for PCI Express core for 7 series FPGA design implementations.
For placement/path information on the integrated block for PCIe itself, the following
constraint can be utilized:
set_property LOC PCIE_X*Y* [get_cells {U0/comp_axi_enhanced_pcie/
comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_inst/
pcie_top_i/pcie_7x_i/pcie_block_i}]
For placement/path information of the GTX transceivers, the following constraint can be
utilized:
set_property LOC GTXE2_CHANNEL_X*Y* [get_cells {U0/comp_axi_enhanced_pcie/
comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_inst/
gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/
gtx_channel.gtxe2_channel_i}]
For placement/path constraints of the input PCIe differential clock source (using the
example provided in
), the following can be utilized:
set_property LOC IBUFDS_GTE2_X*Y* [get_cells {*/PCIe_Diff_Clk_I/
USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUFDS_GTE2_I}]
Constraints for Artix-7 FPGAs
Special consideration must be given to Artix®-7 device implementations. The same IP block
constraint can be used as described previously (see
Constraints for Virtex-7 and Kintex-7
). However, the PCIe serial transceiver wrapper instance is different in the IP.
Use the following LOC constraint for the GTP transceivers in Artix-7 devices.