Manual PCIe-DIO-120/96/72
13
The cards are designed to emulate each GROUP wherein:
a.
There are two 8-bit ports (A and B) and two 4-bit ports (C Hi and C Lo).
b.
Any port can be configured as an input or an output.
c.
Outputs are latched.
d.
Inputs are not latched.
e.
The card is initialized in the input mode
Each GROUP contains a control register. This Write-only, 8-bit register is used to set the
mode and direction of the ports. At Power-Up or Reset, all I/O lines are set as inputs.
Each GROUP should be configured during initialization by writing to the control registers
even if the ports are going to be used as inputs. Output buffers are automatically set by
hardware logic according to the control register states. Control registers are located at
base add3, +7, +B, +F, and +13. Bit assignments in each of these control
registers are as follows:
Bit
Assignment
Function
D0
Port C Lo (C0-C3)
1 = Input, 0 = Output
D1
Port B
1 = Input, 0 = Output
D2
N/A
N/A
D3
Port C Hi (C4-C7)
1 = Input, 0 = Output
D4
Port A
1 = Input, 0 = Output
D5,D6 N/A
N/A
D7
Mode Set (see note 1) Scratchpad
Table 6-2:
Control Register Bit Assignments
Note 1: This bit is a read/write scratchpad. For maximum compatibility with the 8255,
always set this bit (to 1).
Base A1C (read/write) DIO Buffer Enable / Disable (tri-state)
At power-up or reset, all DIO buffers on the card are enabled. To disable the DIO
buffers, write a one to bit 0. To re-enable the DIO buffers, write a zero to bit 0. When
buffers are disabled the pins are tri-stated and biased by the state of the pull up or down
configuration jumpers. A read of bit 0 returns the enable / disable status.
