SERIES PMC470 PCI MEZZANINE CARD
48-CHANNEL DIGITAL I/O MODULE WITH INTERRUPTS
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The default value is 00, setting a 4us debounce period for an 8MHz
debounce clock.
Debounce Clock Select Register
(Enhanced Mode Bank 2, Port 3, Write Only)
This register selects the source clock for the event sense input
debounce circuitry. If bit 0 of this register is 0 (default value), then
the debounce source clock is taken from I/O47 (pin 41 of P1), thus
reducing the effective number of inputs to 47. If bit 0 is set to 1,
then the 8MHz internal system bus clock is used (recommended).
Bits 1-7 of this register are not used and will always read as zero.
Bank Select (Write) & Status (Read) Register 2
(Enhanced Mode Bank 2, Port 7, Read and Write)
Bits 0-5 of this register are not used. Bits 6 & 7 of this register
are used to indicate (read) or select (write) the bank of registers to
be addressed. In Enhanced Mode, three banks (banks 0, 1, & 2) of
eight registers may be addressed. Bank 0 is similar to the Standard
Mode bank of registers. Bank 1 allows the 48 event inputs to be
monitored and controlled. Bank 2 registers control the debounce
circuitry of inputs. Bits 7 and 6 select/indicate the bank as follows:
Bank Select (Write) & Status(Read) Register
Bit 7 Bit 6
BANK OF REGISTERS
00
Bank 0 – Read/Write I/O
01
Bank 1 - Event Status/Clear
10
Bank 2 - Debounce Control, Clock, & Duration
11
INVALID - DO NOT WRITE
INDEPENDENT FIXED FUNCTION CONTROL REGISTERS
Interrupt Enable & Software Reset Register (Read/Write, 23CH)
Bit-0 of this register specifies if the internal event sense
interrupts are to drive INTA# or not. This bit defaults to 0 (interrupt
request disabled) and event interrupts are only flagged internally.
That is, you would have to poll the Event Status Register to
determine if an interrupt had occurred and the INTA# line would not
be driven. If bit-0 of this register is set to “1”, then interrupts will
drive the INTA# line. Note bit-0 of the Interrupt Enable Register is at
Base A 23CH and must always be set to enable interrupts.
This bit is cleared following a system reset, but not a software reset
(see below).
Note, to enable interrupts and the driving of INTA#, you must
also set bit-0 high in the Interrupt Register at Base A000H.
Writing a 1 to the bit-1 position of this register will cause a
software reset to occur (be sure to preserve the current state of bit 0
when conducting a software reset). This bit is not stored and merely
acts as a trigger for software reset generation (this bit will always
readback as 0). The effect of a software reset is similar to a system
reset, except that it only resets the digital ASIC chip that provides
the field interface functions. Likewise, the Interrupt Enable Bit of this
register is not cleared in response to a software reset (these are not
stored in the ASIC). Bits 2-7 of this register are not used and will
always read low (1’s).
THE EFFECT OF RESET
A power-up or bus-initiated software reset will set the outputs to
the false (high) state and place the module in the Standard
Operating Mode (thus disabling debounce and event detection).
Pullups on the I/O lines ensure a false (high) input signal for inputs
left floating (i.e. reads as 0). A reset will also clear the mask register
and enable writes to the I/O ports. Further, all I/O event inputs are
reset, set to negative events, and are disabled following reset.
Another form of software reset (IER register initiated) acts
similar to a system or power-up reset, except that it only resets the
digital ASIC chip installed on the module.
PMC470 PROGRAMMING
To make programming and communicating with the board
easier, Acromag provides a software product (sold separately)
consisting of PMC module VxWorks
libraries. This software
(Model PMCSW-API-VXW, MSDOS format) is composed of
VxWorks
(real time operating system) libraries for all Acromag
PMC modules. The software is implemented as a library of “C”
functions which link with existing user code to make possible simple
control of all Acromag PMC modules.
Acromag, also provides a software product (sold separately)
consisting of PMC module ActiveX (Object Linking and Embedding)
controls for Windows 98, 95
, ME, 2000 and Windows NT
compatible application programs (Model PMCSW- ATX, MSDOS
format) to program and communicate with the board.
Basic I/O Operation
Note that the I/O lines of this module are assembled in groups of
eight. Each group of eight I/O lines is referred to as a port. Ports
0-5 control and monitor I/O lines 0-47. Additionally, ports are
grouped eight to a bank. There are four banks of ports used for
controlling this module (Standard Mode, plus Enhanced Mode
Banks 0, 1, and 2), plus 2 additional registers for enabling the
interrupt request line, generating a software reset, and storing the
interrupt vector.
In both the Standard and Enhanced operating modes, each
group of eight parallel input lines (port) are gated to the data bus
D0..D7 lines. These input signals are inverted--when an output is
ON (set to “1”), the transistor sinks current and drives the output low
(this is readback as a “1”). Inputs include hysteresis. Further, each
input port is connected such that the current status of a given output
port can be read back via the corresponding input port. Individual
ports may also be masked from writes to the port when the port is
intended for input only and this helps prevent contention errors.
Each port I/O line includes an integrated, 47K
Ω
(nominal) pullup
resistor to +5V. Additional 4.7K
Ω
pullup resistor SIP’s are also
installed in sockets on the board. For inputs, the pullups provide a
low (false=0) input indication if the input is left floating.
Each output port clocks the data on D0-D7 into D-type flip-flops.
This data is inverted and drives the I/O line in the form of an open-
drain signal. Thus, data written to any port used as an input must be
masked or always false (zero) to avoid contention errors between the
output circuitry and an input signal from an external device. Note
that flip-flop outputs are buffered onto the I/O line so that external
drivers cannot force a state change in the flip-flop. All 48 output
