Acromag PMC470 Series User Manual Download

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SERIES PMC470 PCI MEZZANINE CARD

48-CHANNEL DIGITAL I/O MODULE WITH INTERRUPTS

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Enhanced Mode Memory Maps

The following table shows the memory maps used for the

Enhanced Mode of operation. Enhanced Mode includes the same
functionality of Standard Mode, but allows each I/O port’s event
sense input and debounce logic to be enabled. Thus, the Enhanced
Mode allows input event triggered interrupts to occur.

In Enhanced Mode, a memory map is given for each of 3

memory banks. The first memory bank (bank 0) has the same
functionality as the Standard Mode. Additionally, its port 7 register is
used to select which bank to access (similar to Standard Mode
where port 7 was used to select the Enhanced Mode). Bank 1
provides read/write access to the 48 event sense inputs. Bank 2
provides access to the registers used to control the debounce
circuitry applied to the event sense inputs.

Table 3.2B: PMC470 R/W Space Address (Hex) Memory Map

HEX
Base
Addr+

MSB

D15 D08

LSB

D07 D00

HEX
Base
Addr+

001

INTERRUPT REGISTER

000

ENHANCED MODE, REGISTER BANK [0] DEFINITION:

201

Not Driven

READ/WRITE - Port 0

I/O Register I/O0-I/O7

200

205

Not Driven

READ/WRITE -Port 1

I/O Register I/O8-I/O15

204

209

Not Driven

READ/WRITE - Port 2

I/O Register I/O16-I/O23

208

20D

Not Driven

READ/WRITE - Port 3

I/O Register I/O24-I/O31

20C

211

Not Driven

READ/WRITE - Port 4

I/O Register I/O32-I/O39

210

215

Not Driven

READ/WRITE - Port 5

I/O Register I/O40-I/O47

214

219

Not Driven

READ/WRITE - Port 6

NOT USED

218

21D

Not Driven

READ - Port 7

READ MASK REGISTER

(Also Current Bank Status)

21C

21D

Not Driven

WRITE - Port 7

WRITE MASK REGISTER

(Also Bank Select Register)

21C

ENHANCED MODE, REGISTER BANK [1] DEFINITION:

201

Not Driven

READ - Port 0

Event Sense Status Reg.

(Port 0 I/O Points 0-7)

200

201

Not Driven

WRITE - Port 0

Event Sense Clear Register

(Port 0 I/O Points 0-7)

200

205

Not Driven

READ - Port 1

Event Sense Status Reg.

(Port 1 I/O Points 8-15)

204

205

Not Driven

WRITE - Port 1

Event Sense Clear Register

(Port 1 I/O Points 8-15)

204

209

Not Driven

READ - Port 2

Event Sense Status Reg.

(Port 2 I/O Points 16-23)

208

209

Not Driven

WRITE - Port 2

Event Sense Clear Register

(Port 2 I/O Points 16-23)

208

20D

Not Driven

READ - Port 3

Event Sense Status Reg.

(Port 3 I/O Points 24-31)

20C

20D

Not Driven

WRITE - Port 3

Event Sense Clear Register

(Port 3 I/O Points 24-31)

20C

211

Not Driven

READ - Port 4

Event Sense Status Reg.

(Port 4 I/O Points 32-39)

210

211

Not Driven

WRITE - Port 4

Event Sense Clear Register

(Port 4 I/O Points 32-39)

210

215

Not Driven

READ - Port 5

Event Sense Status Reg.

(Port 5 I/O Points 40-47)

214

215

Not Driven

WRITE - Port 5

Event Sense Clear Register

(Port 5 I/O Points 40-47)

214

219

Not Driven

READ - Port 6

Event Status for Ports 0-5

and Interrupt Status Reg.

218

219

Not Driven

WRITE - Port 6

Event Polarity Control

218

21D

Not Driven

READ - Port 7

Current Bank Status Reg.

21C

21D

Not Driven

WRITE - Port 7

Event Sense Polarity

Control for Ports 4 & 5

and Bank Select Register

21C

ENHANCED MODE, REGISTER BANK [2] DEFINITION:

201

Not Driven

READ/WRITE - Port 0

Debounce Control Register

(for Ports 0-5)

200

205

Not Driven

READ/WRITE - Port 1

Debounce Duration Reg. 0

(for Ports 0-3)

204

209

Not Driven

READ/WRITE - Port 2

Debounce Duration Reg. 1

(for Ports 4 & 5)

208

20D

Not Driven

WRITE ONLY - Port 3

Debounce Clock Select

(8MHz or I/O47)

20C

211

↓

219

Not Driven

Port 4,5,6

NOT USED

210

↓

218

21D

Not Driven

READ/WRITE - Port 7

Bank Status/Select Register

21C

INDEPENDENT FIXED FUNCTION REGISTERS:

221

↓

239

NOT USED

220

↓

238

23D

Not Driven

READ/WRITE

Interrupt Enable Register

(enables INTREQ0) &

Software Reset Generator

23C

241

↓

2FD

NOT USED

240

↓

2FC

Notes (Table 3.2):

1. Bits 15-8 of these registers are not used. Bits 15-8 will be driven

high (1’s).

2. The PMC will not respond to addresses that are "Not Used".
3. Bits 31-16 of these registers will be read as (0’s).

Summary of Contents for PMC470 Series

Page 1: ...nterrupts USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 2000 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 674 C05A002 retired ...

Page 2: ...fe is involved It is important that the user employ satisfactory overall system design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility 1 0 GENERAL INFORMATION The PCI Mezzanine Card PMC Series PMC470 has 48 channels of general purpose digital inputs and outputs Inputs and outputs of this module are CMOS and TTL compatible Each of the I O lines can be used as eith...

Page 3: ...g controls for Windows 98 95 ME 2000 and Windows NT compatible application programs Model PMCSW ATX MSDOS format This software provides individual controls that allow Acromag PMC modules to be easily integrated into Windows application programs such as Visual C Visual Basic Microsoft Office 97 applications and others The ActiveX controls provide a high level interface to PMC modules eliminating th...

Page 4: ...models and are directly compatible with industry accepted I O panels termination panels and relay racks Consult the factory for information on compatible products I O Noise and Grounding Considerations The PMC470 is non isolated between the logic and field I O grounds since output common is electrically connected to the PMC module ground Consequently the field I O connections are not isolated from...

Page 5: ... PMC470 is a PCI Local Bus Specification version 2 2 compliant PCI bus target only PMC module The carrier CPU connects a PCI host bus to the PMC module The PCI bus is defined to address three distinct address spaces I O memory and configuration space The PMC module can be accessed via the PCI bus memory space and configuration spaces only The PCI card s configuration registers are initialized by s...

Page 6: ...o cover the additional functionality in this mode The first bank of the Enhanced Mode bank 0 is similar in operation to the Standard Mode The second bank bank 1 provides event sense and interrupt control The third bank is used to configure the debounce circuitry to be applied to input channels in the Enhanced Mode Two additional registers are provided to enable the interrupt request line generate ...

Page 7: ...t 0 Event Sense Clear Register Port 0 I O Points 0 7 200 205 Not Driven 1 READ Port 1 Event Sense Status Reg Port 1 I O Points 8 15 204 205 Not Driven 1 WRITE Port 1 Event Sense Clear Register Port 1 I O Points 8 15 204 209 Not Driven 1 READ Port 2 Event Sense Status Reg Port 2 I O Points 16 23 208 209 Not Driven 1 WRITE Port 2 Event Sense Clear Register Port 2 I O Points 16 23 208 20D Not Driven ...

Page 8: ... this register will return the status of the mask The Mask Register is used to disable writes to I O ports designated as input ports Thus when a port group of 8 I O lines is used for input writes to this port must be blocked masked to prevent contention between the output circuitry open drain and any external devices driving this port Standard Mode Write Mask Register Port 7 BIT WRITE TO REGISTER ...

Page 9: ...p Flop Re enable I O5 Event Sense 6 Port 0 I O6 Event Status Clear I O6 Event Sense Flip Flop Re enable I O6 Event Sense 7 Port 0 I O7 Event Status Clear I O7 Event Sense Flip Flop Re enable I O7 Event Sense Event Interrupt Status Register For Ports 0 5 Enhanced Mode Bank 1 Port 6 Read Only Reading this register will return the event interrupt status of I O ports 0 5 bits 0 5 and the interrupt sta...

Page 10: ...o be monitored and controlled Bank 2 registers control the debounce circuitry of the event inputs Bits 7 and 6 select the bank as follows Bank Selected Status Register Read Bit 7 Bit 6 BANK OF REGISTERS 00 Bank 0 Read Write I O 01 Bank 1 Event Status Clear 10 Bank 2 Event Debounce Control Clock and Duration 11 INVALID DO NOT WRITE BANK 2 REGISTERS Debounce Control Register Enhanced Mode Bank 2 Por...

Page 11: ...wer up or bus initiated software reset will set the outputs to the false high state and place the module in the Standard Operating Mode thus disabling debounce and event detection Pullups on the I O lines ensure a false high input signal for inputs left floating i e reads as 0 A reset will also clear the mask register and enable writes to the I O ports Further all I O event inputs are reset set to...

Page 12: ... negative transitions Since channel polarity is programmable on a nibble basis group of four the first nibble of a port could be configured for low to high transitions the second nibble for high to low transitions As such up to 24 change of state detectors may be configured Debounce Control Debounce control is built into the on board digital ASIC employed by the PMC470 and is enabled in the Enhanc...

Page 13: ...time before it will be recognized as a valid input transition Note that Debounce Duration Register 1 port address 2 would be used to configure debounce durations for I O points of ports 4 5 5 Enable the debounce circuitry for port 0 inputs by setting bit 0 of the Debounce Control Register Write 01H to the Port 0 Debounce Control Register at Base Address 200 of this bank If the module had been conf...

Page 14: ... the PMC module will initially terminate with a retry While the read data is moved to the read register typically 1000ns continued retries will result in retry terminations The retry termination allows the PCI bus to be free for other system operations while the data is moved to the read register A PCI bus write to the PMC module will result in 1 immmediately accepting the write data and normal cy...

Page 15: ...V direct contact discharge at input output terminals and European Standard EN50082 1 Electric Fast Transient Immunity EFT Complies with IEC1000 4 4 Level 2 0 5KV at field input and output terminals and European Norm EN50082 1 Radiated Emissions Meets or exceeds European Norm EN50081 1 for class A equipment Warning This is a class A product In a domestic environment this product may cause radio int...

Page 16: ... feet This shielded cable is recommended for all I O applications both digital I O and precision analog I O Application Used to connect Model 5025 552 termination panel to the PMC Module Length Standard lenght is 2 meters 6 56 feet Consult factory for other lenghts It is recommended that this length be kept to a minimum to reduce noise and power loss Cable 50 conductors 28 AWG on 0 050 inch center...

Page 17: ...SERIES PMC470 PCI MEZZANINE CARD 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS ___________________________________________________________________________________________ 17 ...

Page 18: ...SERIES PMC470 PCI MEZZANINE CARD 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS ___________________________________________________________________________________________ 18 ...

Page 19: ...SERIES PMC470 PCI MEZZANINE CARD 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS ___________________________________________________________________________________________ 19 ...

Page 20: ...SERIES PMC470 PCI MEZZANINE CARD 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS ___________________________________________________________________________________________ 20 ...

Page 21: ...SERIES PMC470 PCI MEZZANINE CARD 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS ___________________________________________________________________________________________ 21 ...

Page 22: ...SERIES PMC470 PCI MEZZANINE CARD 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS ___________________________________________________________________________________________ 22 ...

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