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Operation Theory
SSI timing signal
Functionality
SSI_TIMEBASE
SSI master: send the TIMEBASE out
SSI slave: accept the SSI_TIMEBASE to replace the internal
TIMEBASE signal.
Note: Affects on both A/D and D/A operations
SSI_AD_TRIG
SSI master: send the internal AD_TRIG out
SSI slave: accept the SSI_AD_TRIG as the digital trigger
signal.
SSI_ADCONV
SSI master: send the ADCONV out
SSI slave: accept the SSI_ADCONV to replace the internal
ADCONV signal.
SSI_SCAN_START
SSI master: send the SCAN_START out
SSI slave: accept the SSI_SCAN_START to replace the
internal SCAN_START signal.
SSI_DA_TRIG
SSI master: send the DA_TRIG out.
SSI slave: accept the SSI_DA_TRIG as the digital trigger
signal.
SSI_DAWR
SSI master: send the DAWR out.
SSI slave: accept the SSI_DAWR to replace the internal
DAWR signal.
Table 14: Summary of SSI timing signals and the corresponding
functionalities as the master or slave
In PCI form factor, there is a connector on the top right corner of the card
for the SSI. Refer to section 2.3 for the connector position. All the SSI sig-
nals are routed to the 20-pin connector from the FPGA. To synchronize
multiple cards, users can connect a special ribbon cable (ACL-SSI) to all
the cards in a daisy-chain configuration
In PXI form factor, we utilize the PXI trigger bus built on the PXI backplane
to provide the necessary timing signal connections. All the SSI signals are
routed to the P2 connector. No additional cable is needed. For detailed
information of the PXI specifications, please refer to PXI specification Re-
vision 2.0 from PXI System Alliance (www.pxisa.org).
The 6 internal timing signals could be routed to the SSI or the PXI trigger
bus through software drivers. Please refer to section 4.6.1 for detailed i n-
formation of the 6 internal timing signals. Physically the signal routings are
accomplished in the FPGA. Cards that are connected together through the
SSI or the PXI trigger bus, will still achieve synchronization on the 6 timing
s ignals.
