UG-707
ADV8005 Hardware Reference Manual
exosd_format_sel[4:0]
, IO Map,
Address 0x1B68[4:0]
This signal is used to select the input format for the video data.
Function
exosd_format_sel[4:0]
Description
0x00
1 x 8 bit bus 4:2:2
0x01
1 x 10 bit bus 4:2:2
0x02
1 x 12 bit bus 4:2:2
0x03
2 x 8 bit buses 4:2:2
0x04
2 x 10 bit buses 4:2:2
0x05
2 x 12 bit buses 4:2:2
0x06
3 x 8-bit buses, SDR 4:4:4
0x07
3 x 10-bit buses, SDR 4:4:4
0x08
3 x 12-bit buses, SDR 4:4:4
0x09
1 x 8 bit DDR bus 4:2:2
0x0A
1 x 10 bit DDR bus 4:2:2
0x0B
1 x 12 bit DDR bus 4:2:2
0x0C (default)
3 x 8 bit buses 4:4:4
exosd_swap_bus_ctrl[2:0]
, IO Map,
Address 0x1B68[7:5]
This signal is used to control the external OSD input pixel bus. The input pixel bus is 24 bits wide and is divided into three data channels:
Top = D[23:16], Middle = D[15:8] and Bottom = D[7:0]. This register allows the user to swap the order of these three data channels.
Function
exosd_swap_bus_ctrl[2:0]
Description
000 (default)
D[23:16] D[15:8] D[7:0]
001
D[23:16] D[7:0] D[15:8]
010
D[23:16] D[15:8] D[7:0]
011
D[15:8] D[23:16] D[7:0]
100
D[7:0] D[23:16] D[15:8]
101
D[7:0] D[15:8] D[23:16]
110
D[15:8] D[7:0] D[23:16]
111
D[23:16] D[15:8] D[7:0]
The input formatter also has a number of controls which can be used to provide extra flexibility in terms of data processing.
Once a DDR mode is selected using
, the order of the luma and chroma data can be configured using
In DDR modes, the luma is expected on the rising edge of the pixel clock. Setting this bit to 1 swaps the luma and chroma samples and places
the chroma sample (C) on the rising edge and the luma sample (Y) on the falling edge. Refer to
for more information. The edge on
which each sample of DDR data is latched into the part can be specified using
Figure 34: DDR Mode, Luma and Chroma Swap
exosd_ddr_yc_swap
, IO Map,
Address 0x1B6A[0]
This bit is used to swap the Luma (Y) and Chroma (C) data in DDR modes. By default, Y is expected on the rising edge of the clock.
Function
exosd_ddr_yc_swap
Description
0 (default)
Y on rising edge of clock
1
C on rising edge of clock
Y
C
Y
C
Y
C
Y
C
C
Y
C
Y
C
Y
C
Y
ddr_yc_swap = 1
ddr_yc_swap = 0
Y
C
Y
C
Y
C
Y
C
C
Y
C
Y
C
Y
C
Y
ddr_yc_swap = 1
ddr_yc_swap = 0
Rev. A | Page 58 of 317
