Page 2 of 4 - 22 March 2005
Technical specifications are subject to change without prior notice
General description
The MPEG-4 decoder is a hardware module optimized for FPGA technologies, making use of a limited
number of logic resources and being able to decode a 4CIF (704x576) sequence in real time. The
decoder can also be used to decode multiple streams simultaneously (up to 8).
It is compliant with the Video part of ISO/IEC 14496-2. Most of the visual tools of the Simple Profile are
implemented, including support of I-VOP (intra-coded frames, without motion estimation) and P-VOP
(predictive-coded frame, with motion estimation on previously encoded frame).
The following tools are supported:
-
Half pixel motion
-
I-VOP, P-VOP
The following tools are not supported:
-
4MV
-
Error resilience (data partitioning, reversible VLC decoding and slice resynchronization)
-
Short header (on demand the core can be customized to support this)
Supported image resolutions include pre-defined levels Level1 to Level5 (QCIF/CIF/VGA/SDTV) and
custom definitions up to 4CIF (704x576). The core can be customized to provide support for even larger
resolutions, such as HD format.
Applications
•
Video broadcast
•
Security and Surveillance
•
Multimedia streaming over TCP/IP
•
Mobile communications
Technical description
Figure 1 illustrates a simplified block diagram of the BA132MPEG4D IP showing the internal modules and
its interfaces.
The core accepts the compressed stream at its Compressed Data Interface. The stream contains
headers. The decoded video data is organized in macroblocks under YUV format (4:2:0 resolution). One
macroblock is made of 4 luminance blocks (8x8), 1 Cb block (8x8) and 1 Cr block (8x8). The video data
is output by the core through its video interface in macroblock raster scan order.
The decoder has a generic interface to a memory controller, allowing the connection to any custom
memory controller. Thanks to the burst nature of data transfers at this interface, the core can be used
with simple SRAM but also SDRAM or DDR SDRAM. The core can be delivered with a standard SRAM
controller; a suitable SDRAM controller is separately available. The core has been optimized in order to
minimize the amount and bandwidth of off-chip memory. A single frame needs to be stored and
accesses are reduced to 1 read and 1 write per input sample.
The following sections describe the modules constituting the BA132MPEG4D core as depicted under
Figure 1.
Header decoding
This module decodes compliant MPEG-4 VOL and VOP headers (short headers and data partitioning are
not supported but the core can be customized to add these features).
Entropy decoding
The entropy decoder applies a Huffman decoding on both the motion vectors and the compressed pixels.
This module uses pre-defined Huffman tables.
