Designing Hardware for QuickUSB
GPIF Master Mode I/O Models
The QuickUSB module interfaces to target hardware by implementing a number
of I/O models that provide enough flexibility to interface to a wide variety target
hardware. The I/O models are selected by reprogramming the firmware of the
QuickUSB module using the QuickUSB Programmer. Each firmware load
implements a different I/O model. The timing diagrams for each I/O model are
given below.
QuickUSB Signal
I/O Model
FD[15:0] (Word Wide) or FD[7:0] (Byte Wide)
All
IFCLK All
CMD_DATA All
REN or nREN
All
WEN or nWEN
All
nEMPTY
FIFO & Block
nFULL
FIFO & Block
nOE
FIFO & Block
Table 1 – GPIF Master Mode I/O Connections
GPIF Master Mode Timing Parameters
Internally Sourced
IFCLK
Externally
Sourced IFCLK
Parameter
Description
Min
Max
Min
Max
Unit
tIFCLK IFCLK
Period
20.83
20.83 200
ns
tSRY
RDYX to Clock Set-
up Time
8.9
2.9
ns
tRYH
Clock to RDYX Hold
Time
0
3.7
ns
tSGD
GPIF Data to Clock
Set-up Time
9.2
3.2
ns
tDAH
GPIF Data Hold
Time
0
4.5
ns
tSGA
Clock to GPIF
Address
Propagation Delay
7.4
11.4
ns
tXGD
Clock to GPIF Data
Output Propagation
Delay
11 15
ns
tXCTL
Clock to CTLX
Output Propagation
Delay
6.7
10.7
ns
Table 2 – GPIF Master Mode Timing Parameters
6
High Speed Parallel Port
