The SPTEF bit in the S register indicates when the transmit data buffer is ready to accept
new data. The S register must be read when S[SPTEF] is set before writing to the SPI
data register; otherwise, the write is ignored.
Data may be read from the SPI data register any time after S[SPRF] is set and before
another transfer is finished. Failure to read the data out of the receive data buffer before a
new transfer ends causes a receive overrun condition, and the data from the new transfer
is lost. The new data is lost because the receive buffer still held the previous character
and was not ready to accept the new data. There is no indication for a receive overrun
condition, so the application system designer must ensure that previous data has been
read from the receive buffer before a new transfer is initiated.
Address: 4007_6000h base + 5h offset = 4007_6005h
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
SPI0_D field descriptions
Field
Description
Bits[7:0]
Data (low byte)
29.3.6 SPI Match Register (SPIx_M)
This register contains the hardware compare value. When the value received in the SPI
receive data buffer equals this hardware compare value, the SPI Match Flag in the S
register (S[SPMF]) sets.
Address: 4007_6000h base + 7h offset = 4007_6007h
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
SPI0_M field descriptions
Field
Description
Bits[7:0]
Hardware compare value (low byte)
Memory Map and Register Descriptions
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
454
Freescale Semiconductor, Inc.