Chapter 13 Serial Peripheral Interface (S12SPIV5)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
518
Freescale Semiconductor
13.2.3
SS — Slave Select Pin
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when it is configured as a master and it is used as an input to receive the slave select
signal when the SPI is configured as slave.
13.2.4
SCK — Serial Clock Pin
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
13.3
Memory Map and Register Definition
This section provides a detailed description of address space and registers used by the SPI.
13.3.1
Module Memory Map
The memory map for the SPI is given in
. The address listed for each register is the sum of a
base address and an address offset. The base address is defined at the SoC level and the address offset is
defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have
no effect.
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0000
SPICR1
R
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
W
0x0001
SPICR2
R
0
XFRW
0
MODFEN
BIDIROE
0
SPISWAI
SPC0
W
0x0002
SPIBR
R
0
SPPR2
SPPR1
SPPR0
0
SPR2
SPR1
SPR0
W
0x0003
SPISR
R
SPIF
0
SPTEF
MODF
0
0
0
0
W
0x0004
SPIDRH
R
R15
R14
R13
R12
R11
R10
R9
R8
T15
T14
T13
T12
T11
T10
T9
T8
W
0x0005
SPIDRL
R
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
W
0x0006
Reserved
R
W
0x0007
Reserved
R
W
= Unimplemented or Reserved
Figure 13-2. SPI Register Summary
