General Purpose I/O Module
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
13-9
Preliminary
13.6.4
Port Clear Output Data Registers (CLR
n
)
Writing 0s to a CLR
n
register clears the corresponding bits in the PORT
n
register. Writing 1s has no effect.
Reading the CLR
n
register returns 0s.
The CLR
n
registers with a full 8-bit implementation are shown in
n
registers use fewer than eight bits. Their bit definitions are shown in
,
, and
. The fields are described in
, which applies to all CLR
n
registers.
The CLR
n
registers are read/write.
Table 13-4. PORT
n
P/SET
n
Field Descriptions
Field
Description
Port
n
Px
Port
n
x pin data/set data bits.
1 Port
n
Px pin state is “1” (read); writing a 1 sets the corresponding port
n
x bit to “1”
0 Port
n
Px pin state is “0”
IPSBAR
Offsets:
0x10_005C (CLRDD)
0x10_0052 (CLRAN)
Access: User read/write
7
6
5
4
3
2
1
0
R
CLR
n
7
CLR
n
6
CLR
n
5
CLR
n
4
CLR
n
3
CLR
n
2
CLR
n
1
CLR
n
0
W
Reset:
0
0
0
0
0
0
0
0
Figure 13-17. Port Clear Output Data Registers with Bits 7:0 Implemented (CLRDD, CLRAN)
IPSBAR
Offsets:
0x10_0056 (CLRTA)
0x10_0057 (CLRTC)
0x10_0058 (CLRTD)
0x10_0059 (CLRUA)
0x10_005A (CLRUB)
0x10_005B (CLRUC)
Access: User read/write
7
6
5
4
3
2
1
0
R
0
0
0
0
CLR
n
3
CLR
n
2
CLR
n
1
CLR
n
0
W
Reset:
0
0
0
0
0
0
0
0
Figure 13-18. Port Clear Output Data Registers with Bits 3:0 Implemented (CLRTA, CLRTC, CLRTD, CLRUA,
CLRUB, CLRUC)
