System Control Module (SCM)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
13-9
13.5.5
Core Watchdog Service Register (CWSR)
The software watchdog service sequence must be performed using the CWSR as a data register to prevent
a CWT time-out. The service sequence requires two writes to this data register: first a write of 0x55
followed by a write of 0xAA. Both writes must be performed in this order prior to the CWT time-out, but
any number of instructions or accesses to the CWSR can be executed between the two writes. If the CWT
has already timed out, writing to this register has no effect in negating the CWT interrupt.
illustrates the CWSR. At system reset, the contents of CWSR are uninitialized.
13.6
Internal Bus Arbitration
The internal bus arbitration is performed by the on-chip bus arbiter, which containing the arbitration logic
that controls which of up to four MBus masters (M0–M3 in
) has access to the external buses.
The function of the arbitration logic is described in this section.
Figure 13-6. Arbiter Module Functions
13.6.1
Overview
The basic functionality is that of a 2-port, pipelined internal bus arbitration module with the following
attributes:
IPSBAR
Offset: 0x0013 (CWSR)
Access: read/write
7
6
5
4
3
2
1
0
R
CWSR[7:0]
W
Reset: Uninitialized
Figure 13-5. Core Watchdog Service Register (CWSR)
SRAM1
MPARK
RAMBAR
CPU
M0
DMA
M2
M3
FEC
Internal
MARB
Modules
Back door to SRAM and flash
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MCF52235CVM60
