General Purpose I/O Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
14-8
Freescale Semiconductor
14.6.3
Port Pin Data/Set Data Registers (SETn)
The SET
n
registers reflect the current pin states and control the setting of output pins when the pin is
configured for digital I/O.
The SET
n
registers with a full 8-bit implementation are shown in
n
registers use fewer than eight bits. Their bit definitions are shown in
, and
. The fields are described in
, which applies to all SET
n
registers
.
The SET
n
registers are read/write. At reset, the bits in the SET
n
registers are set to the current pin states.
Reading a SET
n
register returns the current state of the port
n
pins.
Writing 1s to a SET
n
register sets the corresponding bits in the PORT
n
register. Writing 0s has no effect.
Table 14-3. DDRn Field Descriptions
Field
Description
DDRnx
Sets data direction for port nx pin when the port is configured as a digital output.
1 DDRnx is configured as an output
0 DDRnx is configured as an input
IPSBAR
Offsets:
0x10_003A (SETAN)
0x10_0044 (SETDD)
0x10_0046 (SETGP)
Access: User read/write
7
6
5
4
3
2
1
0
R
SET
n
7
SET
n
6
SET
n
5
SET
n
4
SET
n
3
SET
n
2
SET
n
1
SET
n
0
W
Reset:
1
1
1
1
1
1
1
1
Figure 14-10. Port Pin Data/Set Data Registers with Bits 7:0 Implemented (SETAN, SETDD, SETGP)
IPSBAR
Offsets:
0x10_003B (SETAS)
0x10_003E (SETTA)
0x10_003F (SETTC)
0x10_0040 (SETTD)
0x10_0041 (SETUA)
0x10_0042 (SETUB)
0x10_0043 (SETUC)
Access: User read/write
7
6
5
4
3
2
1
0
R
0
0
0
0
SET
n
3
SET
n
2
SET
n
1
SET
n
0
W
Reset:
0
0
0
0
1
1
1
1
Figure 14-11. Port Pin Data/Set Data Registers with Bits 3:0 Implemented (SETAS, SETTA, SETTC, SETTD,
SETUA, SETUB, SETUC)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
