General Purpose I/O Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
14-9
14.6.4
Port Clear Output Data Registers (CLRn)
Writing 0s to a CLR
n
register clears the corresponding bits in the PORT
n
register. Writing 1s has no effect.
Reading the CLR
n
register returns 0s.
The CLR
n
registers with a full 8-bit implementation are shown in
n
registers use fewer than eight bits. Their bit definitions are shown in
, and
. The fields are described in
, which applies to all CLR
n
registers.
The CLR
n
registers are read/write.
IPSBAR
Offsets:
0x10_003C (SETQS)
0x10_0045 (SETLD)
Access: User read/write
7
6
5
4
3
2
1
0
R
0
SET
n
6
SET
n
5
SET
n
4
SET
n
3
SET
n
2
SET
n
1
SET
n
0
W
Reset:
0
1
1
1
1
1
1
1
Figure 14-12. Port Pin Data/Set Data Registers with Bits 6:0 Implemented (SETQS, SETLD)
IPSBAR
Offset: 0x10_0038 (SETNQ)
Access: User read/write
7
6
5
4
3
2
1
0
R
SET
n
7
SET
n
6
SET
n
5
SET
n
4
SET
n
3
SET
n
2
SET
n
1
0
W
Reset:
1
1
1
1
1
1
1
0
Figure 14-13. Port NQ Pin Data/Set Data Register (SETNQ)
Table 14-4. SETn Field Descriptions
Field
Description
SETnx
Port n pin data/set data bits.
1 Port n pin x state is 1 (read); writing a 1 sets the corresponding bit to 1
0 Port n pin x state is 0 (read)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
