DMA Controller Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
20-4
Freescale Semiconductor
20.3.1
DMA Request Control (DMAREQC)
The DMAREQC register provides a software-controlled connection matrix for DMA requests. It logically
routes DMA requests from the DMA timers and UARTs to the four channels of the DMA controller.
Writing to this register determines the exact routing of the DMA request to the four channels of the DMA
modules.
If DCR
n
[EEXT] is set and the channel is idle, the assertion of the appropriate external DREQ
n
signal
activates channel
n
.
Table 20-1. DMA Controller Memory Map
IPSBAR
Offset
Register
Width Access
Reset Value
Section/Page
0x00_0014
DMA request control register (DMAREQC)
1
1
Located within the SCM, but listed here for clarity.
32
R/W
0x0000_0000
0x00_0100
+ n * 0x10
Source address register n (SARn)
where n = 0–3
32
R/W
0x0000_0000
0x00_0104
+ n * 0x10
Destination address register n (DARn)
where n = 0–3
32
R/W
0x0000_0000
0x00_0108
+ n * 0x10
DMA status (DSRn) and byte count register n (BCRn)
where n = 0–3
32
R/W
0x0000_0000
0x00_010C
+ n * 0x10
DMA control register n (DCRn)
where n = 0–3
32
R/W
0x0000_0000
IPSBAR
Offset: 0x00_0014 (DMAREQC)
Access: read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
DMAC3
DMAC2
DMAC1
DMAC0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-3. DMA Request Control Register (DMAREQC)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
