DMA Controller Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
20-6
Freescale Semiconductor
20.3.3
Destination Address Registers (DARn)
DAR
n
holds the address to which the DMA controller sends data.
20.3.4
Byte Count Registers (BCRn) and DMA Status Registers (DSRn)
The BCR
n
and DSR
n
registers are two logical registers that occupy one 32-bit register, as shown in
. The address used to access both registers is the same; DSR
n
occupies bits 31–24, and BCR
n
occupies bits 23–0. BCR
n
contains the number of bytes yet to be transferred for a given block. BCR
n
decrements on the successful completion of the address transfer of a write transfer. BCR
n
decrements by
1, 2, 4, or 16 for byte, word, longword, or line accesses, respectively.
The fields of the DSR
n
. In response to an
event, the DMA controller writes to the appropriate DSR
n
bit. Only a write to DSR
n
[DONE] results in
action. DSR
n
[DONE] is set when the block transfer is complete.
IPSBAR
Offset:
0x00_0104 (DAR0)
0x00_0114 (DAR1)
0x00_0124 (DAR2)
0x00_0134 (DAR3)
Access: Read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
DAR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
DAR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-5. Destination Address Registers (DARn)
IPSBAR
Offset:
0x00_0108 (BCR0/DSR0)
0x00_0118 (BCR1/DSR1)
0x00_0128 (BCR2/DSR2)
0x00_0138 (BCR3/DSR3)
Access: Read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
DSR
BCR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
BCR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-6. Byte Count Registers (BCRn) and DMA Status Registers (DSRn)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
