ColdFire Core
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
3-10
Freescale Semiconductor
IC stage until the referenced data is available. As the prefetch data arrives in the IFP, it can be loaded into
the FIFO instruction buffer or gated directly into the OEP.
The V2 design uses a simple static conditional branch prediction algorithm (forward-assumed as
not-taken, backward-assumed as taken), and all change-of-flow operations are calculated by the OEP and
the target instruction address fed back to the IFP.
The IFP and OEP are decoupled by the FIFO instruction buffer, allowing instruction prefetching to occur
with the available core bus bandwidth not used for operand memory accesses. For the V2 design, the
instruction buffer contains three 32-bit locations.
Consider the operation of the OEP for three basic classes of non-branch instructions:
•
Register-to-register:
op
Ry,Rx
•
Embedded load:
op
<mem>y,Rx
•
Register-to-memory (store)
move
Ry,<mem>x
For simple register-to-register instructions, the first stage of the OEP performs the instruction decode and
fetching of the required register operands (OC) from the dual-ported register file, while the actual
instruction execution is performed in the second stage (EX) in one of the execute engines (e.g., ALU,
barrel shifter, divider, EMAC). There are no operand memory accesses associated with this class of
instructions, and the execution time is typically a single machine cycle. See
.
Figure 3-11. V2 OEP Register-to-Register
For memory-to-register (embedded-load) instructions, the instruction is effectively staged through the
OEP twice with a basic execution time of three cycles. First, the instruction is decoded and the components
Operand Execution Pipeline
DS
OC
AG
EX
Opword
Extension 1
Extension 2
Core Bus
Read Data
Core Bus
Address
Core Bus
Write
Data
new Rx
Rx
Ry
RGF
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MCF52235CVM60
