Debug Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
31-4
Freescale Semiconductor
NOTE
Debug control registers can be written by the external development system
or the CPU through the WDEBUG instruction. These control registers are
write-only from the programming model and they can be written through the
BDM port using the
WDMREG
command. In addition, the
configuration/status register (CSR) can be read through the BDM port using
the
RDMREG
command.
The ColdFire debug architecture supports a number of hardware breakpoint registers, that can be
configured into single- or double-level triggers based on the PC or operand address ranges with an optional
inclusion of specific data values.
31.3.1
Shared Debug Resources
The debug module revision A implementation provides a common hardware structure for BDM and
breakpoint functionality. Certain hardware structures are used for BDM and breakpoint purposes as shown
in
Table 31-3. Debug Module Memory Map
DRc[4–0]
Register Name
Width
(bits)
Access
Reset Value
Section/
Page
0x00
Configuration/status register (CSR)
32
R/W
See Note
0x0090_0000
0x05
BDM address attribute register (BAAR)
32
1
1
Each debug register is accessed as a 32-bit register; reserved fields are not used (don’t care).
W
0x05
0x06
Address attribute trigger register (AATR)
32
W
0x0005
0x07
Trigger definition register (TDR)
32
W
0x0000_0000
0x08
PC breakpoint register 0 (PBR0)
32
W
Undefined
0x09
PC breakpoint mask register (PBMR)
32
W
Undefined
0x0C
Address breakpoint high register (ABHR)
32
W
Undefined
0x0D
Address breakpoint low register (ABLR)
32
W
Undefined
0x0E
Data breakpoint register (DBR)
32
W
Undefined
0x0F
Data breakpoint mask register (DBMR)
32
W
Undefined
0x18
PC breakpoint register 1 (PBR1)
32
W
See Section
0x1A
PC breakpoint register 2 (PBR2)
32
W
See Section
0x1B
PC breakpoint register 3 (PBR3)
32
W
See Section
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MCF52235CVM60
