Enhanced Direct Memory Access (eDMA)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
12-19
Preliminary
12.3.2.16 Transfer Control Descriptor (TCD)
Each channel requires a 32-byte transfer control descriptor for defining the desired data movement
operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel
1,... channel 15. The definitions of the TCD are presented as eight 32-bit values.
of the basic TCD structure.
n
structure.
Table 12-17. EDMA_CPRn Field Descriptions
Field
Description
ECP
Enable Channel Preemption.
0 Channel n cannot be suspended by a higher priority channel’s service request.
1 Channel n can be temporarily suspended by the service request of a higher priority channel.
bits 1–3
Reserved.
CHPRI
Channel n Arbitration Priority. Channel priority when fixed-priority arbitration is enabled. The reset value
for the channel priority fields CHPRI[0–3], is equal to the corresponding channel number for each priority
register; that is, EDMA_CPR31[CHPRI] = 0b1111.
Table 12-18. TCDn 32-bit Memory Structure
eDMA Offset
TCDn Field
(32 x n)+0x0000
Source address (saddr)
(32 x n)+0x0004
Transfer attributes
Signed source address offset (soff)
(32 x n)+0x0008
Inner minor byte count (nbytes)
(32 x n)+0x000C
Last source address adjustment (slast)
(32 x n)+0x0010
Destination address (daddr)
(32 x n)+0x0014
Current major iteration count (citer)
Signed destination address offset (doff)
0x1000 (32 x n) 0x0018
Last destination address adjustment / scatter-gather address (dlast_sga)
(32 x n)+0x001c
Beginning major iteration count (biter)
Channel control/status
