Miscellaneous Control Module (MCM)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
16-14
Freescale Semiconductor
Preliminary
16.2.2.5.7
Flash ECC Data Register (FEDR)
The FEDR is a 32-bit register for capturing the data associated with the last, properly-enabled ECC event
in the flash memory. Depending on the state of the ECC configuration register, an ECC event in the flash
causes the address, attributes and data associated with the access to be loaded into the FEAR, FEMR,
FEAT, and FEDR registers and also the appropriate flag (FNCE) in the ECC status register to be asserted.
The data captured on a multi-bit non-correctable ECC error is undefined.
Since the Flash performs ECC checking on a 64-bit double word, the 32-bit word captured in the FEDR
register may not be the word that contained the error.
This register is read-only; any attempted write is ignored. See
for the flash
ECC data register definition.
16.2.2.5.8
RAM ECC Address Register (REAR)
The REAR is a 32-bit register for capturing the address of the last, properly-enabled ECC event in the
RAM memory. Depending on the state of the ECC configuration register, an ECC event in the RAM causes
the address, attributes and data associated with the access to be loaded into the REAR, RESR, REMR,
REAT, and REDR registers and also the appropriate flag (RNCE) in the ECC status register to be asserted.
This register is read-only; any attempted write is ignored. See
for the RAM
ECC address register definition.
Offset:
MCM_BAS 0x005C
Access: User read only
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
FEDR
W
Reset
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
FEDR
W
Reset
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Figure 16-11. Flash ECC Data (FEDR) Register
Table 16-12. FEDR Field Descriptions
Field
Description
FEDR
Flash ECC Data Register. Contains the data associated with the faulting access of the last, properly-enabled
flash ECC event. The register contains the data value taken directly from the data bus.
