Deserial Serial Peripheral Interface (DSPI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
23-26
Freescale Semiconductor
Preliminary
23.3.2.11 DSPI DSI Serialization Data Register (DSPI_SDR)
The DSPI_SDR contains the signal states of the parallel input signals from the eMIOS. The pin states of
the parallel input signals are latched into the DSPI_SDR on the rising edge of every system clock. The
Table 23-11. DSPI_DSICR Field Descriptions
Field
Description
bits 0–11
Reserved.
TXSS
Transmit Data Source Select. Selects the source of data to be serialized. The source can be data from host
software written to the DSPI DSI alternate serialization data register (DSPI_ASDR) or parallel output pin states
latched into the DSPI DSI serialization data register (DSPI_SDR).
0 Source of serialized data is the DSPI_SDR
1 Source of serialized data is the DSPI_ASDR
bits 13–14
Reserved.
CID
Change in Data Transfer Enable. Enables a change in serialization data to initiate a transfer. The bit is used in
master mode in DSI and CSI configurations to control when to initiate transfers. When the CID bit is set,
serialization is initiated when the current DSI data differs from the previous DSI data shifted out. The
DSPI_COMPR is compared with the DSPI_SDR or DSPI_ASDR to detect a change in data. Refer to
Section 23.4.4.5, “DSI Transfer Initiation Control
,” for more information.
0 Change in data transfer operation disabled
1 Change in data transfer operation enabled
DCONT
DSI Continuous Peripheral Chip Select Enable. Enables the PCSx signals to remain asserted between transfers.
The DCONT bit affects the PCS signals in DSI master mode only. See
Section 23.4.8.5, “Continuous Selection
,” for details.
0 Return peripheral chip select signals to their inactive state after transfer is complete
1 Keep peripheral chip select signals asserted after transfer is complete
DSICTAS
DSI Clock and Transfer Attributes Select. The DSICTAS field selects which of the DSPI_CTARs is used to provide
transfer attributes in DSI configuration. The DSICTAS field is used in DSI master mode. In DSI slave mode, the
DSPI_CTAR1 is always selected. The table below shows how the DSICTAS values map to the DSPI_CTARs.
bits 20–25
Reserved.
DPCSn
DSI Peripheral Chip Select n. The DPCS bits select which of the PCSx signals to assert during a DSI transfer.
The DPCS bits control the assertions of the PCSx signals in DSI master mode only.
0 Negate PCSn
1 Assert PCSn
DSICTAS
DSI Clock and Transfer Attributes
Controlled by
000
DSPI_CTAR0
001
DSPI_CTAR1
010
DSPI_CTAR2
011
DSPI_CTAR3
100
DSPI_CTAR4
101
DSPI_CTAR5
110
DSPI_CTAR6
111
DSPI_CTAR7
