FlexRay Communication Controller (FLEXRAY)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
30-8
Freescale Semiconductor
Preliminary
30.4.1
Oscillator Clocking
If the protocol engine is clocked by the internal crystal oscillator, an 40 MHz crystal or 40 MHz CMOS
compatible clock must be connected to the oscillator pins. The crystal or clock must fulfil the requirements
given by the
FlexRay Communications System Protocol Specification, Version 2.1 Rev A.
The PLL predivider has to be configured for divide-by-2 operation.
30.4.2
PLL Clocking
If the protocol engine is clocked by the internal PLL
1
, the frequency of the PE clock source is
system clock / 2. The system clock frequency must be 80 MHz.
30.5
Memory Map and Register Description
The FlexRay block occupies 768 bytes of address space starting at the FlexRay block’s base address
defined by the memory map of the MCU.
30.5.1
Memory Map
The complete memory map of the FlexRay block is shown in
. The addresses presented here are
the offsets relative to the FlexRay block base address, which is defined by the MCU address map.
1. Due to the tight timing requirements and overall system requirements of FlexRAY systems, usage of the PLL as the clock
source has not been fully evaluated. It is recommended to use a 40 MHz crystal for the clock source.
Table 30-3. FlexRay Memory Map (Sheet 1 of 4)
Offset from
FLEXRAY_BASE
(0xFFFD_8000)
Register
Access
Module Configuration and Control
0x0000
R
0x0002
Module Configuration Register (MCR)
R/W
0x0004
System Memory Base Address High Register (SYMBADHR)
R/W
0x0006
System Memory Base Address Low Register (SYMBADLR)
R/W
0x0008
Strobe Signal Control Register (STBSCR)
R/W
0x000A
Reserved
R
0x000C
Message Buffer Data Size Register (MBDSR)
R/W
0x000E
Message Buffer Segment Size and Utilization Register (MBSSUTR)
R/W
Test Registers
0x0010
Reserved
R
0x0012
Reserved
R
Interrupt and Error Handling
0x0014
Protocol Operation Control Register (POCR)
R/W
0x0016
Global Interrupt Flag and Enable Register (GIFER)
R/W
0x0018
Protocol Interrupt Flag Register 0 (PIFR0)
R/W
0x001A
Protocol Interrupt Flag Register 1 (PIFR1)
R/W
