Frequency Modulated Phase Locked Loop (FMPLL)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
4-11
Preliminary
4.4
Functional Description
The FMPLL module contains the frequency modulated phase lock loop (FMPLL), enhanced frequency
divider (ERFD), enhanced synthesizer control registers (ESYNCR1 and ESYNCR2), synthesizer status
register (SYNSR), and clock/PLL control logic. The block also contains a reference frequency pre-divider
controlled by the EPREDIV bits in the ESYNCR1. This enables the user to use a high frequency crystal
or external clock generator and obtain finer frequency synthesis resolution than would be available if the
raw input clock were used directly by the analog loop. For the remainder of this chapter, the term
“reference frequency” and the symbol F
ref
indicate the output of the pre-divider circuit. This is the clock
on which frequency multiplication will be performed.
4.4.1
General
At reset, the system clock is driven by the internal oscillator (16 MHz IRC) and the module is in bypass
mode. After reset, software can change the PLL mode (see
Section 4.5.1, “Clock Mode Selection
shows the PLL-clock to input-clock frequency relationships for the available clock modes.
4.4.2
PLL Off Mode
When PLL Off mode is selected, the PLL is off and either the 16 MHz IRC must be selected as the system
clock or the user must supply an external clock or crystal on the EXTAL pin, and select that clock source
before entering PLL Off mode. The selected clock is directly used to produce the various system clocks.
Refer to
MPC5510 Microcontroller Family Data Sheet
for external clock input requirements. In bypass
mode, the analog portion of the PLL is disabled, the frequency modulation capability is not available, and
no clocks are generated at the PLL output. The pre-divider is bypassed and has no effect on the system
clock frequency in bypass mode.
4.4.3
Normal Mode
When normal PLL mode is selected, the PLL is fully programmable. The PLL can synthesize frequencies
ranging from 48x to 148x the reference frequency of the output of the predivider. with or without
frequency modulation enabled. The post-divider is capable of reducing the PLL clock frequency without
forcing a re-lock. The PLL reference can be a crystal oscillator reference or an external clock reference.
This clock will be divided by the pre-divider circuit to create the PLL reference clock.
4.4.3.1
PLL Lock Detection
The lock detect logic monitors the reference frequency and the PLL feedback frequency to determine when
frequency lock has been achieved. Phase lock is inferred by the frequency relationship, but is not
Table 4-11. Clock-Out vs. Clock-In Relationships
Clock Mode
Frequency Equation
Normal PLL Mode
F
sys
F
extal
EMFD
16
+
(
)
•
EPREDIV
1
+
(
)
ERFD
1
+
(
)
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