Frequency Modulated Phase Locked Loop (FMPLL)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
4-18
Freescale Semiconductor
Preliminary
4.5
Resets
This section describes the reset operation of the PLL, including power-on reset and normal resets. The
reset values of registers and signals are provided in other sections.
4.5.1
Clock Mode Selection
The initial clock mode is reflected in the MODE, PLLSEL, and PLLREF bits of the synthesizer status
register (SYNSR) as well as the ESYNCR1[CLKCFG] bit field. The clock mode can be modified by
writing to the CLKCFG bit field. The synthesizer status register will then reflect the newly-selected PLL
clock mode.
shows the clock mode encoding.
The clock mode selection configuration is summarized in
4.5.1.1
Power-On Reset (POR)
The PLL will not operate until the POR signal has negated and the CLKCFG set for PLL mode. Refer to
MPC5510 Microcontroller Family Data Sheet
for these thresholds. At this point, the PLL will operate in
self-clocked mode (SCM) until a valid reference clock is detected by the internal clock monitor circuit.
Internal to the PLL, the VCO will be held in reset until the negation of the POR signal. This prevents the
PLL from attempting to lock before its supplies are within specification which can cause VCO/loop gain
to be lower than what the analog loop is designed for.
4.5.1.2
External Reset
After POR has negated, the PLL defaults to Bypass mode and the default clock source for the system clock
is the 16 MHz IRC. After reset exit, the PLL may be configured for operation and after lock may be
selected as the system clock source.
After the initial lock with the default MFD (assuming normal mode was selected), ESYNCR1 may be
written to modify the MFD for the desired operating frequency. The PLL might not lock with an MFD and
crystal frequency combination that attempts to force the VCO outside its operating range.
Table 4-13. Clock Mode Selection
Clock Mode
Synthesizer Status Register (SYNSR)
MODE, PLLSEL, and PLLREF Bits
MODE/
CLKCFG2
PLLSEL/
CLKCFG1
PLLREF/
CLKCFG0
Bypass mode
0
X
X
Normal mode with external reference
1
1
0
Normal mode with crystal reference
1
1
1
Reserved
1
0
0
