MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor
20-21
20.3.2.5
DSPI DMA/Interrupt Request Select and Enable Register (DSPIx_RSER)
The DSPI
x
_RSER serves two purposes. It enables flag bits in the DSPI
x
_SR to generate DMA requests or
interrupt requests. The DSPI
x
_RSER also selects the type of request to be generated. See the individual
bit descriptions for information on the types of requests the bits support. The user must not write to the
DSPI
x
_RSER while the DSPI is running.
14
RFDF
Receive FIFO drain flag: indicates that the RX FIFO can be drained. Provides a method for the
DSPI to request that entries be removed from the RX FIFO. The bit is set while the RX FIFO
is not empty. The RFDF bit can be cleared by writing 1 to it or by an acknowledgement from
the eDMA controller when the RX FIFO is empty.
0 RX FIFO is empty
1 RX FIFO is not empty
Note: In the interrupt service routine, RFDF must be cleared only after the DSPIx_POPR
register is read.
15
—
Reserved.
16–19
TXCTR
[0:3]
TX FIFO counter. Indicates the number of valid entries in the TX FIFO. The TXCTR is
incremented every time the DSPI _PUSHR is written. The TXCTR is decremented every time
an SPI command is executed and the SPI data is transferred to the shift register.
20–23
TXNXTPTR
[0:3]
Transmit next pointer. Indicates which TX FIFO Entry will be transmitted during the next
transfer. The TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO
to the shift register. See
Section 20.4.3.4, “Transmit First In First Out (TX FIFO) Buffering
” for more details.
24–27
RXCTR
[0:3]
RX FIFO counter. Indicates the number of entries in the RX FIFO. The RXCTR is decremented
every time the DSPI _POPR is read. The RXCTR is incremented after the last incoming databit
is sampled, but before the tASC delay starts. Refer to
Section 20.4.7.1, “Classic SPI Transfer
” for details.
28–31
POPNXTPTR
[0:3]
Pop next pointer. Contains a pointer to the RX FIFO entry that will be returned when the
DSPIx_POPR is read. The POPNXTPTR is updated when the DSPIx_POPR is read. See
Section 20.4.3.5, “Receive First In First Out (RX FIFO) Buffering Mechanism
” for more details.
Table 20-6. DSPIx_SR Field Descriptions (Continued)
Bits
Name
Description
Summary of Contents for MPC5553
Page 5: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 2 Freescale Semiconductor...
Page 21: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 xvi Freescale Semiconductor...
Page 47: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 1 26 Freescale Semiconductor...
Page 163: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 4 20 Freescale Semiconductor...
Page 179: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 5 16 Freescale Semiconductor...
Page 561: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 13 38 Freescale Semiconductor...
Page 615: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 14 54 Freescale Semiconductor...
Page 707: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 17 68 Freescale Semiconductor...
Page 755: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 18 48 Freescale Semiconductor...
Page 873: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 19 118 Freescale Semiconductor...
Page 984: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 Freescale Semiconductor 21 41...
Page 985: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 21 42 Freescale Semiconductor...
Page 1019: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 22 34 Freescale Semiconductor...
Page 1129: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 25 90 Freescale Semiconductor...
