Queued Serial Multi-Channel Module
MPC561/MPC563 Reference Manual, Rev. 1.2
15-6
Freescale Semiconductor
15.4
QSMCM Global Registers
The QSMCM global registers contain system parameters used by the QSPI and dual SCI submodules for
interfacing to the CPU and the intermodule bus. The global registers are listed in
.
15.4.1
Low-Power Stop Operation
When the STOP bit in QSMCMMCR is set, the IMB3 clock input to the QSMCM is disabled and the
module enters a low-power operating state. QSMCMMCR is the only register guaranteed to be readable
while STOP is asserted. The QSPI RAM is not readable in low-power stop mode. However, writes to RAM
or any register are guaranteed valid while STOP is asserted. STOP can be written by the CPU and is cleared
by reset.
System software must bring each submodule to an orderly stop before setting STOP to avoid data
corruption. The SCI receiver and transmitter should be disabled after transfers in progress are complete.
The QSPI can be halted by setting the HALT bit in SPCR3 and then setting STOP after the HALTA flag
is set in SPSR.
15.4.2
Freeze Operation
The FRZ1 bit in QSMCMMCR determines how the QSMCM responds when the IMB3 FREEZE signal
is asserted. FREEZE is asserted when the CPU enters background debug mode. Setting FRZ1 causes the
QSPI to halt on the first transfer boundary following FREEZE assertion. FREEZE causes the SCI1
transmit queue to halt on the first transfer boundary following FREEZE assertion.
15.4.3
Access Protection
The SUPV bit in the QMCR defines the assignable QSMCM registers as either supervisor-only data space
or unrestricted data space.
When the SUPV bit is set, all registers in the QSMCM are placed in supervisor-only space. For any access
from within user mode, the IMB3 address acknowledge (AACK) signal is asserted and a bus error is
generated.
Table 15-2. QSMCM Global Registers
Access
1
1
S = Supervisor access only
S/U = Supervisor access only or unrestricted user access (assignable data space).
Address
MSB
2
0
2
8-bit registers reside on 8-bit boundaries. 16-bit registers reside on 16-bit boundaries.
LSB
15
S
0x30 5000
QSMCM Module Configuration Register (QSMCMMCR)
See <XrefBlue>Table 15-4 for bit descriptions.
T
0x30 5002
QSMCM Test Register (QTEST)
S
0x30 5004
Dual SCI Interrupt Level (QDSCI_IL)
See <XrefBlue>Table 15-5 for bit descriptions.
Reserved
S
0x30 5006
Reserved
Queued SPI Interrupt Level (QSPI_IL)
See <XrefBlue>Table 15-6 for bit descriptions.
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
