Enhanced Queued Analog-to-Digital Converter (EQADC)
Freescale Semiconductor
27-57
PXR40 Microcontroller Reference Manual, Rev. 1
Control Unit
to arbitrate which triggered CFIFO will transfer the next command. ADC commands are
encoded inside the least significant 26 bits of the command message.
A Result message is composed of an RFIFO header and an ADC Result. The
FIFO Control Unit
decodes
the information contained in the RFIFO header to determine the RFIFO to which the ADC result should
be sent. An ADC result is always 16 bits long.
27.7.2.2.1
Message Formats for On-Chip ADC Operation
This section describes the Command/Result message formats used for on-chip ADC operation.
Conversion Command Format for the Standard Configuration
describes the format for conversion commands when interfacing with the on-chip ADCs in the
standard configuration. The standard configuration is selected when the least significant byte (bits 24-31)
of the conversion command is set to zero. In the standard configuration, the conversion result is always
routed to one of the RFIFOs. A time stamp information can be optionally requested.
Conversion Command Format for the Standard Configuration
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
EOQ PAUSE REP RESERVED
EB
(0b0)
BN
CAL
MESSAGE_TAG
LST
TSR FMT
W
CFIFO Header
ADC Command
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
CHANNEL_NUMBER
0
0
0
0
0
0
0
0
W
ADC Command
Table 27-32. Field Descriptions
Field
Description
0
EOQ
End Of Queue Bit. The EOQ bit is asserted in the last command of a CQueue to indicate to the EQADC
that a scan of the CQueue is completed. EOQ instructs the EQADC to reset its current CFIFO transfer
counter value (TC_CF) to zero. Depending on the CFIFO mode of operation, the CFIFO status will also
change upon the detection of an asserted EOQ bit on the last transferred command - see
, for details.
0 Not the last entry of the CQueue.
1 Last entry of the CQueue.
Note: If both the PAUSE and EOQ bits are asserted in the same command message the respective flags
are set, but the CFIFO status changes as if only the EOQ bit were asserted.
1
PAUSE
Pause Bit. The Pause bit allows software to create sub-queues within a CQueue. When the EQADC
completes the transfer of a command with an asserted Pause bit, the CFIFO enters the WAITING FOR
TRIGGER state. Refer to
Section 27.7.4.7.1, CFIFO Operation Status
, for a description of the state
transitions. The Pause bit is only valid when CFIFO operation mode is configured to single or
continuous-scan edge trigger mode.
0 Do not enter WAITING FOR TRIGGER state after transfer of the current Command Message.
1 Enter WAITING FOR TRIGGER state after transfer of the current Command Message.
Note: If both the PAUSE and EOQ bits are asserted in the same command message the respective flags
are set, but the CFIFO status changes as if only the EOQ bit were asserted.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
