Device Performance Optimization
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
33-4
33.3.2
Frequency Modulated PLL
33.3.2.1
Description
The Frequency Modulated Phase Locked Loop (FMPLL) allows the user to generate high speed system
clocks from a crystal oscillator or external clock generator. Further, the FMPLL
supports programmable frequency modulation of the system clock. This module is typically configured
early in the initialization code to ensure satisfactory performance levels are achieved.
33.3.2.2
Recommended configuration
The default operating frequency of the PXR40 device is 2 to 3 times the crystal reference frequency
depending on the state of the PLL configuration pins as reset negates. Typically, the system frequency is
increased shortly after reset negates to provide acceptable performance.
Chapter 6, Frequency Modulated
provides details on how the frequency modulated phase locked loop
(FMPLL) should be initialized in an application. The maximum frequency of operation for this device is
specified in the
PXR40 Microcontroller Data Sheet
.
System performance cannot be linearly extrapolated with system frequency, as is often the expectation. It
is due to the insertion of additional Flash wait states as system frequency increases that system
performance does not scale linearly. Take care to ensure that the correct internal and/or external Flash
configuration is chosen for the selected system frequency. The specific flash access times to be applied are
detailed in
Section 12.2.2.8, Flash Bus Interface Configuration Register (FLASH_BIUCR).
33.3.3
Flash Bus Interface Unit
33.3.3.1
Description
The Flash Bus Interface Unit (FBIU) interfaces the system bus to the Flash memory array controller. The
FBIU contains prefetch buffers and a prefetch controller which, if enabled, speculatively prefetches
sequential lines of data from the Flash array into the buffer. Prefetch buffer hits allow zero-wait state
responses.
The Flash Bus Interface Configuration Registers (BIUCRx) control access to the internal Flash array. Its
settings define the number of cycles required to access the array, access times, and how the prefetch
buffering scheme operates.
Following negation of reset and execution of the BAM, the instruction and data prefetching is disabled,
and the number of cycles required to access the internal Flash array is set to its maximum value of fifteen
additional wait states.
33.3.3.2
Recommended configuration
As the operating frequency of the device is set by configuring the FMPLL (see
), the number of cycles required to access the internal array should be configured
accordingly. Note that the Flash BIUCRx registers cannot be altered by code executing from the Flash
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
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Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
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