FlexRay Communication Controller (FLEXRAY)
Freescale Semiconductor
22-125
PXR40 Microcontroller Reference Manual, Rev. 1
22.6.9.3
FIFO Periodic Timer
The FIFO periodic timer is used to generate an FIFO almost-full interrupt at certain point in time, if the
almost-full watermark is not reached, but the FIFO is not empty. This can be used to prevent frames from
get stuck in the FIFO for a long time.
The FIFO periodic timer is configured via the
Receive FIFO Periodic Timer Register (RFPTR)
. If the
periodic timer duration RFPTIR[PTD] is configured to 0x0000, the periodic timer is continuously expired.
If the periodic timer duration RFPTIR[PTD] is configured to 0x3FFF, the periodic timer never expires. If
the periodic timer is configured to a value
ptd,
greater than 0x0000 and smaller 0x3FFF, the periodic timer
expires and is restarted at the start of every communication cycle, and expires and is restarted after
ptd
macroticks have been elapsed.
22.6.9.4
FIFO Reception
The FIFO reception is a controller internal operation.
A message frame reception is directed into the FIFO, if no individual message buffer is assigned for
transmission or subscribed for reception for the current slot. In this case the FIFO filter path shown in
is activated.
If the FIFO filter path indicates that the received frame has to be appended to the FIFO and the FIFO is
not full, the controller writes the received frame header into the message buffer header field indicated by
the controller internal FIFO write index. The frame payload data are written into the corresponding
message buffer data field. If the status of the received frame indicates a valid non-null frame, the slot status
information is written into the message buffer header field and the controller internal FIFO write index is
updated by 1 and the fifo fill level FLA (FLB) in the
Receive FIFO Fill Level and POP Count Register
is incremented.If the status of the received frame indicates an invalid or null frame, the frame
is not appended to the FIFO.
22.6.9.5
FIFO Almost-Full Interrupt Generation
If the fifo fill level FLA (FLB) is updated after a frame reception and exceeds the FIFO watermark level
WM, i.e. FLA>WM
A
(FLB>WM
B
), then the FIFO almost-full interrupt flag GIFER[FAFAIF]
(GIFER[FAFBIF]) is asserted.If the periodic timer expires, and FIFOA (FIFOB) is not empty, i.e. FLA>0
(FLB>0), then the FIFO almost-full interrupt flag GIFER[FAFAIF] (GIFER[FAFBIF]) is asserted.
22.6.9.6
FIFO Overflow Error Generation
If the FIFOA (FIFOB) is full, i.e. FLA=FIFO_DEPTH
A
(FLB=FIFO_DEPTH
B
) and the conditions for a
FIFO reception as described in
Section 22.6.9.4, FIFO Reception
, are fulfilled, then the fifo overflow error
flag CHIERFR[FOVA_EF] (CHIERFR[FOVB_EF]) is asserted.
22.6.9.7
FIFO Message Access
The FIFOA (FIFOB) contains valid messages if the FIFO fill level FLA (FLB) is greater than 0. The
Receive FIFO A Read Index Register (RFARIR)
(
Receive FIFO B Read Index Register (RFBRIR)
pointing to a message buffer with valid content and the oldest frames stored in the FIFO.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
