FlexCAN Module
24-12
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
24.3.3
Rx FIFO Structure
When the FEN bit is set in the FLEXCAN_x_MCR, the memory area from 0x80 to 0xFC (which is
normally occupied by MBs 0 to 7) is used by the reception FIFO engine.
data structure. The region 0x80-0x8C contains an MB structure which is the port through which the CPU
reads data from the FIFO (the oldest frame received and not read yet). The region 0x90-0xDC is reserved
for internal use of the FIFO engine. The region 0xE0-0xFC contains an 8-entry ID table that specifies
filtering criteria for accepting frames into the FIFO.
shows the three different formats that the
elements of the ID table can assume, depending on the IDAM
field of the FLEXCAN_x_MCR. Note that
all elements of the table must have the same format. See
for more information.
0
3
7
8
9
10
11
12
13
14
15
16
23
24
31
0x80
S
R
R
I
D
E
R
T
R
LENGTH
TIME STAMP
0x84
ID (Standard/Extended)
ID (Extended)
0x88
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
0x8C
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
0x90
Reserved
to
0xDC
0xE0
ID Table 0
0xE4
ID Table 1
0xE8
ID Table 2
0xEC
ID Table 3
0xF0
ID Table 4
0xF4
ID Table 5
0xF8
ID Table 6
0xFC
ID Table 7
= Unimplemented or Reserved
Figure 24-3. Rx FIFO Structure
Summary of Contents for PXR4030
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