32
Intel
®
Xeon
®
Processor Specification Update
Errata
P12
Processor may live-lock if PDEs or PTEs are in UC space
Problem:
The processor may livelock under the following boundary conditions:
•
The page-directory entries (PDEs) or page-table entries (PTEs) are in uncacheable (UC) space.
•
An instruction fetch misses the ITLB resulting in a page walk.
•
This instruction fetch is immediately followed by a store that splits a page boundary.
Implication:
When this erratum occurs, the processor will livelock. This erratum was found using random
instruction testing and has not been observed with commercial software.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Table of Changes
.
P13
Thermal status log bit may not be set when the thermal control circuit is
active
Problem:
Bit 1 of the IA32_THERM_STATUS register (Thermal Status Log) is a sticky bit designed to be
set to '1' if the thermal control circuit (TCC) has been active since either the previous processor
reset or software cleared this bit. If TCC is active and the Thermal Status Log bit is cleared by a
processor reset or by software, it will remain clear (set to ‘0’) as long as the TCC remains active.
Once TCC deactivates, the next activation of the TCC will set the Thermal Status Log bit.
Implication:
When this erratum occurs, the Thermal Status Log bit will be cleared (set to ‘0’) although the
thermal control circuit is active.
Workaround:
None at this time.
Status:
For the steppings affected, see the
Summary Table of Changes
.
P14
Processor may timeout waiting for a device to respond after 0.67 seconds
Problem:
The PCI 2.1 target initial latency specification allows two seconds for a device to respond during
initialization-time. The processor may timeout after only approximately 0.67 seconds. When the
processor times out it will hang with IERR# asserted. PCI devices that take longer than 0.67
seconds to initialize may not be initialized properly.
Implication:
System may hang with IERR# asserted.
Workaround:
None at this time.
Status:
For the steppings affected, see the
Summary Table of Changes
.
P15
Cascading of performance counters does not work correctly when forced
overflow is enabled
Problem:
The performance counters are organized into pairs. When the CASCADE bit of the CCCR is set, a
counter that overflows will continue to count in the other counter of the pair. The FORCE_OVF bit
forces the counters to overflow on every non-zero increment. When the FORCE_OVF bit is set, the
counter overflow bit will be set but the counter no longer cascades.
Implication:
The performance counters do not cascade when the FORCE_OVF bit is set.
Workaround:
None at this time.
Status:
For the steppings affected, see the
Summary Table of Changes
.
P16
EMON event counting of x87 loads may not work as expected
Problem:
If a performance counter is set to count x87 loads and floating-point (FP) exceptions are unmasked,
the FPU Operand (Data) Pointer (FDP) may become corrupted.
