46
Intel
®
Xeon
®
Processor Specification Update
Errata
P66
Locks and SMC detection may cause the processor to temporarily hang
Problem:
The processor may temporarily hang in an HT Technology enabled system if one logical processor
executes a synchronization loop that includes one or more bus locks and is waiting for release by
the other logical processor. If the releasing logical processor is executing instructions that are
within the detection range of the self modifying code (SMC) logic, then the processor may be
locked in the synchronization loop until the arrival of an interrupt or other event.
Implication:
If this erratum occurs in an HT Technology enabled system, the application may temporarily stop
making forward progress. Intel has not observed this erratum with any commercially available
software.
Workaround:
None at this time.
Status:
For the steppings affected, see the Summary of Table of Changes.
P67
Incorrect debug exception (#DB) may occur when a data breakpoint is set
on a FP instruction
Problem:
The default Microcode Floating Point Event Handler routine executes a series of loads to obtain
data about the
FP
instruction that is causing the FP event. If a data breakpoint is set on the
instruction causing the FP event, the load in the microcode routine will trigger the data breakpoint
resulting in a debug exception (#DB).
Implication:
An incorrect #DB may occur if data breakpoint is placed on an
FP
instruction. Intel has not
observed this erratum with any commercially available software or system.
Workaround:
None at this time.
Status:
For the steppings affected, see the Summary of Table of Changes.
P68
Modified cache line eviction from L2 cache may result in write back of stale
data
Problem:
It is possible for a modified cache line to be evicted from the L2 cache just prior to another update
to the same line by software. In rare circumstances, the processor may accrue two bus queue entries
that have the same address but have different data. If an external snoop is generated in a narrow
timing window, the data from the older eviction may be used to respond to the external snoop.
Implication:
In the event that this erratum occurs, the contents of memory will be incorrect. This may result in
application, operating system, or system failure
.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary of Table of Changes.
P69
xAPIC may not report some illegal vector errors
Problem:
The local xAPIC has an error status register, which records all errors. The bit 6 (the Receive Illegal
Vector bit) of this register, is set when the local xAPIC detects an illegal vector in a received
message. When an illegal vector error is received on the same internal clock that the error status
register is being written (due to a previous error), bit 6 does not get set and illegal vector errors are
not flagged.
Implication:
The xAPIC may not report some illegal vectors errors when they occur at approximately the same
time as other xAPIC errors. The other xAPIC errors will continue to be reported.
Workaround:
None at this time.
Status:
For the steppings affected, see the Summary of Table of Changes.
