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ADwin-Gold
Hardware Manual, Version 2.3
ADwin
9.4 Mode Pulse Width and Period Width Measurement
In this operating mode an internal reference clock generator clocks the counter
with a signal frequency of 20 MHz or (after a prescaler) 5 MHz. All counters
have a switch in order to change the signal frequency. The period duration or
pulse width of a square-wave signal at input CLR/LATCH can be measured.
In this mode you have to consider at high frequencies that your
GLOBALDELAY
remains smaller than a signal period, in order to acquire a cycle.
9.4.1 Period Duration Measurement
All four counters can execute period duration measurements.
In this mode, the counter values are latched into latch A at every positive edge,
and the previous data are overwritten. The pulse width will be derived from the
counter value difference multiplied by the period duration of the reference clock.
Programming example
Initialize
disable counter
clear counter
mode internal reference clock at internal CLK
input of the counter ...
... with 20 MHz or
... with 5 MHz
set input CLR/LATCH to LATCH-mode
enable counter
read out latch register A
evaluate counter values in program
G
20 or 5 MHz
Control-Registers
32 bit Counter #1...#4
32 bit Latch A (#1...#4)
CLK
EN
CLR
ADwin-GOLD
bus
Data
Data
LATCH
DIR
Up
4k7
Reference clock generator
INIT:
CNT_ENABLE(0)
CNT_CLEAR(1)
CNT_MODE(1)
CNT_INPUTMODE(1)
CNT_ENABLE(1)
CNT_SET(0)
. . .
. . .
CNT_SET(1)
EVENT:
CNT_READLATCH(1)
. . .
9.4.1 Period Duration Measurement
