LatticeMico32 Microprocessor Software Support
LatticeMico GPIO
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LatticeMico32 Microprocessor Software Support
This section describes the software support provided for the LatticeMico
GPIO component, including the GPIO usage model, its relationship with the
LatticeMico32 microprocessor, the device driver, and services. It also
provides software usage examples.
The support routines for the GPIO component are for use in a single-threaded
environment. If used in a multi-tasking environment, re-entrance protections
must be provided.
Usage Model
The GPIO component, as the name suggests, is general-purpose. This
component can be used for the following:
An output device (output mode only)
An input device (input mode only)
An output and input device (output and input mode), which means using
separate input and output pins
A bidirectional device, which means that the same sets of pins are used
for input and output by controlling the direction of the pins
Additionally, this device is capable of generating interrupt requests when the
following are detected on an input port:
High level
Positive edge
Negative edge
The usage scenario depends on the end-user application and does not fit
within a well-known usage model. To handle interrupt from a GPIO that is
configured to trigger interrupts on edge detection, you can disable the
interrupt and perform processing later, since the edge-capture register
remains set on detecting the appropriate condition. Or, you can perform the
processing in the ISR and write a zero to the corresponding bit of the edge-
capture register to clear the condition. In the former case, the edge-capture
register is cleared when the interrupt is enabled again; in the latter case, the
edge-capture register is explicitly cleared by writing a zero to the
corresponding bit of the edge-capture register.
Effect of Endianness
LatticeMico32 is a big-endian microprocessor. Therefore, it is important to
understand the impact of endianness when the microprocessor interacts with
the component's registers. In a big-endian architecture, the most-significant
byte of a multi-byte object is stored at the lowest address, and the least-
significant byte of that object is stored at the highest address.
