PIC32 Family Reference Manual
DS61104E-page 17-50
© 2007-2011 Microchip Technology Inc.
17.5.20 ADC Sampling Requirements
The analog input model of the 10-bit ADC module is shown in
. The total acquisition
time for the analog-to-digital conversion is a function of the internal amplifier settling time and the
holding capacitor charge time.
For the ADC module to meet its specified accuracy, the charge holding capacitor (C
HOLD
) must
be allowed to fully charge to the voltage level on the analog input pin. The analog output source
impedance (R
S
), the interconnect impedance (R
IC
), and the internal sampling switch (R
SS
)
impedance combine to directly affect the time required to charge the C
HOLD
. The combined
impedance of the analog sources must therefore be small enough to fully charge the holding
capacitor within the chosen sample time. After the analog input channel is selected (changed),
this acquisition function must be completed prior to starting the conversion. The internal holding
capacitor will be in a discharged state prior to each sample operation.
A time period of at least 1 T
AD
should be allowed between conversions for the acquisition time.
Refer to the
“Electrical Characteristics”
section in the specific device data sheet for more
information.
Figure 17-22: 10-bit ADC Analog Input Model
17.5.21 Connection Considerations
Since the analog inputs employ Electrostatic Discharge (ESD) protection, they have diodes to
V
DD
and V
SS
. This requires that the analog input must be between V
DD
and V
SS
. If the input
voltage exceeds this range by greater than 0.3V (in either direction), one of the diodes becomes
forward-biased and it may damage the device if the input current specification is exceeded.
An external RC filter is sometimes added for anti-aliasing of the input signal. The R component
should be selected to ensure that the acquisition time requirements are satisfied. Any external
components connected (through high-impedance) to an analog input pin (capacitor, Zener diode,
etc.) should have very little leakage current at the pin.
C
PIN
VA
Rs
ANx
V
T
= 0.6V
V
T
= 0.6V
I
LEAKAGE
R
IC
≤
250
Ω
Sampling
Switch
R
SS
C
HOLD
= DAC capacitance
V
SS
V
DD
= 4.4 pF
±
500 nA
Note:
The C
PIN
value depends on the device package and is not tested. The effect of the C
PIN
is negligible if Rs
≤
5 k
Ω
.
R
SS
≤
3 k
Ω
Legend:
C
PIN
= input capacitance
V
T
= threshold voltage
R
SS
= sampling switch resistance
R
IC
= interconnect resistance
R
S
= source resistance
C
HOLD
= sample/hold capacitance
I
LEAKAGE
= leakage current at the pin due to various junctions
