IGLOO2 FPGA Adaptive FIR Filter Demo Guide
Revision 2
33
Table 1
describes SmartDesign blocks in Adaptive FIR Filter.
Table 2
describes SmartDesign blocks in LMS_FIR_TOP.
Table 1 •
Adaptive FIR Filter Demo SmartDesign Blocks and Description
S.No
Block Name
Description
1
DATAHANDLE_0
Handles communication between the Host PC and IGLOO2 Evaluation Kit board.
2
FILTERCONTROL_FSM_
0
Control logic to generate the control signals for FIR and FFT operations.
3
LMS_FIR_TOP
SmartDesign.
4
INPUT_Buffer
FIR input signal data buffer.
OUTPUT_Buffer
FIR output signal buffer.
FFT_Im_Buffer
FFT output imaginary data buffer.
FFT_Re_Buffer
FFT output real data buffer.
5
COREFFT_0 COREFFT
IP.
6
SYSRESET_0
Reset IP.
7
OSC_0
Oscillator IP.
8
FCCC_0
Clock conditioning circuit IP.
Table 2 •
LMS_FIR_TOP SmartDesign Blocks and Description
S.No
Block Name
Description
1
LMS_ALGO
LMS algorithm implemented in the RTL to compute error, correction factor, and
filter coefficients.
2
LMS_CONTROL_FSM
FSM implemented in the RTL to control LMS_ALGO block.
3
COREFIR
COREFIR IP.
Superseded
