Index
6527 Register-Level Programmer Manual
I-2
ni.com
FE<7..0> bits, Filter Interval Registers, 2-8
Filter Enables (Ports 0–2) Register, 2-8
Filter Interval Registers, 2-7
FL<19..0> bits, Filter Interval Registers, 2-7
G
general operation registers
Clear Register, 2-6
ID Register, 2-5
Input Registers (Ports 0–2), 2-3
Output Registers (Ports 3–5), 2-4
overview, 1-2
register address map (table), 2-1
H
handling interrupts, 3-8
I
ID Register, 2-5
ID<7..0> bits, ID Register, 2-5
initializing PCI local bus, 3-2 to 3-5
for Macintoshes, 3-4 to 3-5
for PCs, 3-2 to 3-4
input, programming, 3-5 to 3-6
with filtering, 3-6
Input Registers (Ports 0–2), 2-3
interrupt generation, configuring, 3-7 to 3-8
interrupts, handling, 3-8
M
manual.
See
documentation.
Master Interrupt Control Register,
2-10 to 2-11
MasterInterruptEnable bit, Master Interrupt
Control Register, 2-10
MasterInterruptStatus bit, Change Status
Register, 2-9
N
N.
<7..0> bits
Input Registers (Ports 0–2), 2-3
Output Registers (Ports 3–5), 2-4
NI Developer Zone, A-1
O
output, programming, 3-6
Output Registers (Ports 3–5), 2-4
Overflow bit, Change Status Register, 2-9
OverflowIntEnable bit, Master Interrupt
Control Register, 2-11
P
PCI local bus, initializing, 3-2 to 3-5
for Macintoshes, 3-4 to 3-5
for PCs, 3-2 to 3-4
PCI MITE Application-Specific Integrated
Circuit (ASIC), 1-1
PCI-6527 digital I/O device.
See
6527 device.
Ports 0–2
Falling-Edge Detection Registers
(Ports 0–2), 2-13
Filter Enables (Ports 0–2) Register, 2-8
Input Registers (Ports 0–2), 2-3
Rising-Edge Detection Registers
(Ports 0–2), 2-12
Ports 3–5 (Output Registers), 2-4
programming.
See also
registers.
common terms, 3-1 to 3-2
digital I/O circuitry, 3-5 to 3-8
change notification, 3-7 to 3-8
configuring interrupt generation,
3-7 to 3-8
disabling, 3-8
handling interrupts, 3-8
input, 3-5 to 3-6
with filtering, 3-6
output, 3-6
