Software Introduction
14
SLWU055A – May 2008 – Revised May 2016
Copyright © 2008–2016, Texas Instruments Incorporated
TSW3070EVM: Amplifier Interface to Current Sink DAC - Arbitrary Waveform
Generator Demonstration
Table 3. Software Feature Descriptions (continued)
Control Name
Input/Output
Description
Fab
Output
Fab where the DAC5682Z was manufactured.
EVM Serial
Number
Output
Serial number of the EVM.
Status Messages
Output
Displays the status of the communication session.
USB/READBACK BOX
Reset USB Port
Input
Begins a new USB session. Press this if you see a status error message.
Readback
Input/Output
Disables DAC5682Z register reads (simulation mode)
DAC5682Z REGISTER TABLE BOX
Register Table
Output
Displays the DAC5682Z register configuration.
DAC5682Z REGISTER CONFIGURATION BOX
PLL SETTINGS
PLL
Input/Output
When disabled, the PLL is bypassed
PLL Sleep
Input/Output
When set, the PLL is put into sleep mode.
PLL Lock
Output
Turns green when the internal PLL is locked.
PLL Reset
Input/Output
When set, the PLL loop filter is pulled down to 0V. Toggle to restart the PLL if an over-speed
lock-up occurs.
VCO Frequency
Input/Output
When set to 2x, the PLL clock output is 1/2 the PLL VCO frequency. Used to run the VCO at
2X the needed clock frequency to reduce phase noise for lower input clock rates.
PLL Gain (MHz/V)
Input/Output
Used to adjust the PLL Voltage Controlled Oscillator (VCO) gain.
PLL Range (MHz)
Input/Output
Sets the PLL VCO frequency range.
M value
Input/Output
M portion of the M/N divider of the PLL.
N value
Input/Output
N portion of the M/N divider of the PLL. This value should be chosen to divide down the input
CLKIN to maintain a maximum PFD of 160 MHz.
DLL SETTINGS
DLL
Input/Output
When disabled, the DLL is bypassed and the LVDS data source is responsible for providing
correct setup and hold timing.
DLL Sleep
Input/Output
When set, the DLL is put into sleep mode.
Auto-DLL
Input
When set, the DLL is restarted automatically when there is a change in the DLL settings, so
there is no need to press the DLL restart control.
DLL Lock
Output
Turns green when the internal DLL is locked.
DLL restart
Input/Output
Restarts the DLL
DLL Delay (deg.)
Input/Output
Used to manually adjust the DLL delay
＝
from the DLL fixed current delay.
DLL fixed current
delay (ps/µA)
Input/Output
Adjusts the DLL delay line bias current. Used in conjunction with the DLL inv clock to select
appropriate delay range for a given DCLK frequency
DLL inv clock
Input/Output
Used to invert the internal DLL clock to force convergence to a different solution. This can be
used in the case where the DLL delay adjustment has exceeded the limits of its range
INPUT SETTINGS
format
Input/Output
Selects between 2’s complement and offset binary formats.
reverse bus
Input/Output
When enabled, reverses the LVDS input data bus so that the MSB to LSB order is swapped.
swap data
Input/Output
When enabled, the A/B data paths are swapped prior to routing to the DACA and DACB
outputs.
same data
Input/Output
When enabled, the data routed to DACA is also routed to DACB.
FIFO offset
Input/Output
Sets the FIFO’s output pointer location, allowing the input pointer to be shifted –4 to +3
positions upon SYNC. Default offset is 0 and is updated upon each sync event.
DIGITAL SETTINGS
digital logic
Input/Output
Enables the interpolation filters on the device.
interpolation
Input/Output
Selects the interpolation rate.
CM0 mode
Input/Output
Determines the mode of FIR0 and CMIX0 blocks. Since CMIX0 is located between FIR0 and
FIR1, its output is half-rate. Settings apply to both A and B channels.
CM1 mode
Input/Output
Determines the mode of FIR1 and final CMIX1 blocks. Settings apply to both A and B
channels.
