NXP Semiconductors
AN10815
SWIM: NXP's basic graphics library for LPC products
separate power domain, and NAND Flash and DDR memory controllers. These features
make the devices particularly suitable for automotive and industrial control applications
as well as medical systems.
5.1 Description of Phytec board setup
The LPC3250 Phytec is shipped with a preinstalled bootloader called the stage 1 loader
(S1L). It is assumed that this is present on the board. The S1L first initializes the board
with the code from the phy3250_startup_entry.s and phy3250_startup.c files before
starting the monitor program. Without this initialization the colorbar example will not run.
Be sure to configure your system defines in phy3250_board.h to match your hardware
revisions. Failure to properly set these defines to the correct value may prevent the code
from working correctly.
The possible define values are below:
PHY3250_CARRIERBOARD_1305_X
PHY3250_MODULEBOARD_1304_X
PHY3250_LCD_1307_X
LCD modules have a board number of 1307.x, where x = 0 or 1. The change between .0
and .1 LCD module is detailed below:
LCD module revision differences:
.0
initial
board
.1
Active HIGH backlight signal, different wiring
Because of differences in the connector wiring of ‘.0’ and ’.1’ LCD modules, the ‘.0’ LCD
modules should only be used with ‘.0’ carrier boards, while ‘.1’ LCD modules should only
be used with ’.2’ or greater carrier boards.
Carrier boards have a revision number of 1305.x, where x = 0 to 3. The changes
between the boards module are shown below:
Carrier board revision differences:
.0/.1
Initial
board
.2/.3
USB peripheral VBUS routed to USB_VBUS signal
.2/.3
GPI4 used to VBUS detection for USB peripheral
.2/.3
USB_ADR/SW used to control USB_ host power
Module boards have a revision number of 1304.x, where x = 0 to 1. The changes
between the module boards module are shown below:
Module board revision differences:
.0
Initial
board
.1
USB ISP1301 I2C address changed from 0x2C to 0x2D
For correct jumper settings please refer to the PHYTEC phyCORE-LPC3250 System on
Module and Carrier Board Hardware Manual.
The phyCORE-LPC3250 board comes preconfigured with 64 MB of 133 MHz SDR
SDRAM configured for 32-bit access using two 16-bit wide RAM chips at U10 and U11.
The LPC3250 is capable of addressing a single RAM bank located at memory address
0x8000 0000 and extending to 0x9FFF FFFF via the /DYCS0 signal.
AN10815
© NXP B.V. 2011. All rights reserved.
Application note
Rev. 3 — 15 June 2011
11 of 20
