Audio Interface Module (AIM)
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
17-17
Bits are ordered first bit left. So, C-channel bit “0” is seen in bit position 31 in the EBURcvCChannel
register. C-channel bit “31” is seen as the LSB bit in the register.
17.6.1.3
Control Channel Interrupt (IEC958 “C” Channel New Frame)
When the value of a new IEC958 “C” channel frame is loaded into the EBURcvCChannel register, an
interrupt is generated. This interrupt is cleared when the processor writes the corresponding bit in the
InterruptClear register. EBURcvCChannel is double buffered. However the register can be read at any time
and provide true values the interrupt only indicates that a NEW “C” channel value has been loaded.
17.6.1.4
Validity Flag Reception
An interrupt is associated with the Validity flag. (interrupt 24 - IEC958ValNoGood). This interrupt is set
every time a frame is seen on the IEC958 interface with the validity bit set to “invalid”.
17.6.1.5
IEC958 Exception Definition
There are several IEC958 exceptions defined that will trigger an interrupt. These are:
•
Control channel change—Set when EBURcvCChannel register is updated. The register is updated
for every new C-Channel received. The exception is reset when EBURcvCChannel register is read.
•
EBU Illegal Symbol—Set on reception of illegal symbol during IEC958 receive. Reset by writing
register InterruptClear. Refer to
Section 17.7.7, “Audio Interrupts
”
for details. The EBU input is a
biphase/mark modulated signal. The time between any two successive transitions of the EBU
signal is always 1, 2 or 3 EBU symbol periods long. The EBU receiver will parse the stream, and
split it in so-called symbols. It recognizes s1, s2 and s3 symbols, depending on the length of the
symbols. Not all sequences of these symbols are allowed. To give an example, a sequence
s2-s1-s1-s1-s2 cannot occur in a error-free EBU signal. If the receiver finds such an illegal
sequence, the
illegal symbol
interrupt is set. No corrective action is undertaken.
When the interrupt occurs, this means:
a) The EBU signal is has been affected by noise
Address MBAR2 + 0X24 (EBU1RCVCCHANNEL)
MBAR2 + 0XD4 (EBU2RCVCCHANNEL)
Access: User read only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
EBURcvC Channel1 and Channel2
W
Reset
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
EBURcvC Channel1 and Channel2
W
Reset
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Figure 17-9. EBURcvCChannel Register
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
