UM10147_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 28 April 2008
60 of 134
NXP Semiconductors
UM10147
P89LPC952/954 User manual
5
SM2_0
Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or
3, if SM2 is set to 1, then Rl will not be activated if the received 9th data bit (RB8)
is 0. In Mode 0, SM2 should be 0. In Mode 1, SM2 must be 0.
6
SM1_0
With SM0 defines the serial port mode, see
7
SM0_0/
FE_0
The use of this bit is determined by SMOD0 in the PCON register. If SMOD0 = 0,
this bit is read and written as SM0, which with SM1, defines the serial port mode. If
SMOD0 = 1, this bit is read and written as FE (Framing Error). FE is set by the
receiver when an invalid stop bit is detected. Once set, this bit cannot be cleared
by valid frames but is cleared by software. (Note: UART0 mode bits SM0_0 and
SM1_0 should be programmed when SMOD0 is logic 0 - default mode on any
reset.)
Table 52.
Serial Port 1 Control register (S1CON - address B5h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
SM0_0/F
E_1
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
Reset
x
x
x
x
x
x
0
0
Table 53.
Serial Port 1 Control register (S1CON - address B5h) bit description
Bit Symbol
Description
0
RI_1
Receive interrupt flag 1. Set by hardware at the end of the 8th bit time in Mode 0,
or approximately halfway through the stop bit time in Mode 1. For Mode 2 or Mode
3, if SMOD0, it is set near the middle of the 9th data bit (bit 8). If SMOD0 = 1, it is
set near the middle of the stop bit (see SM2_1 - S1CON.5 - for exceptions). Must
be cleared by software.
1
TI_1
Transmit interrupt flag 1. Set by hardware at the end of the 8th bit time in Mode 0,
or at the stop bit (see description of INTLO_1 bit in S1STAT register) in the other
modes. Must be cleared by software.
2
RB8_1
The 9th data bit that was received in Modes 2 and 3. In Mode 1 (SM2 must be 0),
RB8_1 is the stop bit that was received. In Mode 0, RB_1 is undefined.
3
TB8_1
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software
as desired.
4
REN_1
Enables serial reception. Set by software to enable reception. Clear by software to
disable reception.
5
SM2_1
Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or
3, if SM2 is set to 1, then Rl_1 will not be activated if the received 9th data bit
(RB8_1) is 0. In Mode 0, SM2_1 should be 0. In Mode 1, SM_1 must be 0.
6
SM1_1
With SM0_1 defines the serial port mode, see
7
SM0_1/
FE_1
The use of this bit is determined by SMOD0 in the PCON register. If SMOD0 = 0,
this bit is read and written as SM0_1, which with SM1_1, defines the serial port
mode. If SMOD0 = 1, this bit is read and written as FE_1 (Framing Error). FE_1 is
set by the receiver when an invalid stop bit is detected. Once set, this bit cannot be
cleared by valid frames but is cleared by software. (Note: UART1 mode bits
SM0_1 and SM1_1 should be programmed when SMOD0 is logic 0 - default mode
on any reset.)
Table 51.
Serial Port 0 Control register (S0CON - address 98h) bit description
…continued
Bit Symbol
Description
