Pentek 52791, Getting Started Manual

Model 52791 Getting Started Guide

Page 13

Rev.  1.0

Step 6: Using the Software

ReadyFlow Software

The 

User’s Guide

 for each ReadyFlow BSP provides instructions for using the Ready

−

Flow software. Chapter 3 provides the following:
• Introduction to ReadyFlow  

−

 Provides an overview of how the software is used.

• Using ReadyFlow 

−

 Provides details about using ReadyFlow, along with a modified 

code snippet from the example program.

• Using Linked Lists 

−

 Describes how to set up ADC Trigger Controller Linked Lists 

along with a code snippet from an example program.

Chapter 4 describes the ReadyFlow data structures and routines that access the Linux 

or Windows device driver functions.
Chapter 5 describes Command Line use and operation.
Chapter 6 describes Signal Analyzer use and operation.

GateFlow FPGA Design Kit

Chapter 2 of the 

GateFlow User Manual

 covers procedures for implementing a project:

• Using Your GateFlow FPGA Design Kit with Xilinx’s ISE Design Suite Software
• Preparing for a New FPGA Configuration
• Transferring Configuration Data to the Model 71791

The GateFlow FPGA Design Kit includes test bench files and simulation projects that 

functionally simulate many operations of the Model 71791 XMC module, when the 

FPGAs are configured with their factory default configurations. Details are provided in 

Chapter 3 of the 

GateFlow User Manual

 (see Documentation Required for Installation).

We recommend that before attempting any operational modifications of the default 

FPGA design, you should become very familiar with the board’s performance when 

operated with the default design.  Once you are comfortably familiar with the default 

operation, we recommend that your first project with the FPGA design kit should be to 

re

−

compile the default code with one very simple change (the contents of the read

−

only FPGA Revision registers), and re

−

configure the FPGA with the re

−

compiled con

−

figuration file. (Refer to Chapter 2 of the 

GateFlow User Manual

 for details.)

If you discover that you can use the entire default design for the FPGA, and simply 

need to add another function or two, Table 1

−

2 in Chapter 1 of the 

GateFlow User Man

−

ual

 will help you to determine how much of the FPGA’s resources remain available for 

your use.