PixeLINK Advanced CSRs
51
PixeLINK PL-A780
Document No.: 04646-01
MACHINE VISION CAMERA
SYSTEM GUIDE
Copyright © 2004 PixeLINK
All Rights Reserved
Offset
Name
Field
Bit
Description
Clear_Buffer [1]
Clear buffer (automatically reset)
1 = Clear buffer
Setting this bit will empty the buffer so
that it can be filled with another frame.
This bit will be cleared once the buffer
is reset.
[2..31]
Reserved
mode
22Ch Sync
Cycle
Time
Value [0..31]
Value of the 1394 cycle time that when
reached will cause the camera to
capture a frame. This is only used in
trigger mode 15. A value of
0xFFFFFFFF in this register means the
camera will not begin output of a frame
until a valid value is programmed.
230h
..
2FCh
Reserved for future Feature Control registers.
GPO CONTROL REGISTERS
On_Off [0]
GPO 0 On/Off
1 = On, 0 = Off
Polarity [1]
GPO 0 Polarity
1 = Active High, 0 = Active Low
[2..23]
Reserved
300h
GPO 0 Config
Mode
[24..31]
GPO 0 Mode
.. ..
..
..
..
On_Off [0]
GPO X On/Off
1 = On, 0 = Off
Polarity [1]
GPO X Polarity
1 = Active High, 0 = Active Low
[2..23]
Reserved
300h +
X*4
GPO X Config
Mode
[24..31]
GPO X Mode
.. ..
..
..
..
On_Off [0]
GPO 14 On/Off
1 = On, 0 = Off
Polarity [1]
GPO 14 Polarity
1 = Active High, 0 = Active Low
[2..23]
Reserved
338h
GPO 14 Config
Mode
[24..31]
GPO 14 Mode
33Ch
..
7FFh
Reserved for future Advanced Feature Control Registers
NOTE 1:
The Feature_Id field of the Advanced Feature Access Control Register is a 48bit value with the
following format:
0 – 7
8 – 15
16 – 23
24 – 31
32 – 39
40 - 47