Accessing the RTC is accomplished by first writing the index address to I/O port
address 70H. The valid index address range is 0-7FH. The first 40H locations are
used by the V5C, while the remaining 40H are available for general use. The
register or RAM data can then either be written or read at I/O port address 71H. The
specific use of clock registers is covered in the data sheet on the Motorola 146818A.
Notice:
The RTC clock is a 100-year device. No hardware provisions exist to
denote the rollover in the year 2000. An attempt to circumvent this problem has
been implemented in the BIOS. However, advanced operating systems such as
Windows NT do not use the BIOS to interface to the RTC. As such, they may
display the year 2000 as the year 1900, etc.
The V5C uses the Simtek© STK14C88, 32-pin 32k x 8 Non Volatile SRAM.
The NVSRAM has the ability to store data indefinately without the need for
batteries or other power sources.
The Reset Control Register is used to configure the sources and effects of reset
conditions. The register is located at I/O address 2A0H.
Bit 0:
From VME SYSRST buffer to UNI SYSRST input control. Enables reset
from the VMEbus.
Bit 1:
Enables bit 2A0[7] to cause reset. This bit must be set before 2A0[7] is
set and must remain set when 2A0[7] is set.
Bit 2:
Indicates reset ocurred from 2A0[7]. Write 1 to clear.
Bit 3:
System Reset or Power up indicator.
Bit 4:
From UNI SYSRST to VME. Enables reset to the VMEbus.
Bit 5:
Reserved
Bit 6:
Reset VME via Universe IIB control. VMERST will cause the Universe
chip to assert VXSYSRST while bit 4 is set. Bit 4 must be cleared to de-assert
VMERST.
Bit 7:
Setting this bit causes an equivalent to a front panel reset if 2A0[1] has
been set in a prior write.
NOTE: To clear the 0x2A4[7,5,4] bits, read 0x2a4, shift right 1 bit and write to
0x2A0 to clear.
PC/AT Devices Programming
6-3
Non-Volatile RAM
Reset Control Register
Figure 6-1
Reset Control Register (I/O 2A0H)
7 6 5 4 3 2 1 0
RST
VRSTU
RSV
FPSR SYSRST RST
RSTEN ENVME
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