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SiFive E300 Platform Reference Manual, Version 1.0.1
The counter is incremented at a maximum rate determined by the watchdog clock selection. Each
cycle, the counter can be conditionally incremented depending on the existence of certain condi-
tions, including always incrementing or incrementing only when the processor is not asleep.
The counter can also be reset to zero depending on certain conditions, such as a successful write
to
wdogfeed
or the counter matching the compare value.
Watchdog Clock Selection
The WDT unit clock,
wdogclk
, is either driven from LFXOSC or LFRCOSC and runs at approxi-
mately 32 kHz.
Watchdog Configuration Register
wdogcfg
R
eserve
d
31
29
wdogcmpip
28
R
eserve
d
27
14
wdogencoreawake
13
wdogenalways
12
R
eserve
d
11 10
wdogzerocmp
9
wdogrsten
8
R
eserve
d
7
4
wdogscale
3
0
Figure 8.2: Watchdog configuration register
wdogcfg
The
wdogen*
bits control the conditions under which the watchdog counter
wdogcount
is incre-
mented. The
wdogenalways
bit if set means the watchdog counter always increments. The
wdogencoreawake
bit if set means the watchdog counter increments if the processor core is not
asleep. The WDT uses the
corerst
signal from the wakeup sequencer to know when the core is
sleeping. The counter increments by one each cycle only if any of the enabled conditions are true.
The
wdogen*
bits are reset on AON reset.
The 4-bit
wdogscale
field scales the watchdog counter value before feeding it to the comparator.
The value in
wdogscale
is the bit position within the
wdogcount
register of the start of a 16-bit
wdogs
field. A value of 0 in
wdogscale
indicates no scaling, and
wdogs
would then be equal to
the low 16 bits of
wdogcount
. The maximum value of 15 in
wdogscale
corresponds to dividing the
clock rate by
2
15
, so for an input clock of 32.768 kHz, the LSB of
wdogs
will increment once per
second.
The value of
wdogs
is memory-mapped and can be read as a single 16-bit value over the AON
TileLink bus.
The
wdogzerocmp
bit, if set, causes the watchdog counter
wdogcount
to be automatically reset to
zero one cycle after the
wdogs
counter value matches or exceeds the compare value in
wdogcmp
.
This feature can be used to implement periodic counter interrupts, where the period is independent
of interrupt service time.
The
wdogrsten
bit controls whether the comparator output can set the
wdogrst
bit and hence
cause a full reset.
The
wdogcmpip
interrupt pending bit can be read or written.
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