C 8 0 5 1 F 9 7 0 D K - U G
Rev. 0.1
11
5.10. I2C Slave (H7)
The I2C Slave header provides ground, SDA, and SCL to enable connection to another board with an I2C master.
A 4.7 k
Ω
pull-up is populated by default on both SDA and SCL.
5.11. External Clocks (U6, Y1, Y2)
The C8051F970 target board is equipped with a Silicon Labs Si504 programmable CMEMS oscillator and two
crystal footprints Y1 and Y2. Y1 is a 25 MHz crystal that is populated by default. More information on the Si504 can
be found on the Silicon Labs CMEMS website:
5.12. UART Connection Options (JP1-2, U5)
The target board features a USB virtual COM port (VCP) UART connection via the standard USB connector (J9).
The VCP connection uses the CP210x USB-to-UART bridge chip (U5). The GPIO pins connected to the CP210x
device can be enabled or disabled through the JP1 and JP2 headers. Table 2 shows the GPIO pins that are routed
to the CP210x.
5.13. Port Pin Headers (H1-6)
All of the MCU port pins are available on the 0.100-inch headers on target board. Each connector provides
connections to each port, VDD, and ground. Any unused pins on the
Port 5
header are not connected. Some of
these port pins are shared with other functions on the board and may be modified as explained in Section 5.14.
Table 2. CP210x Controlled GPIO Pins
MCU Pin
COM Function
P0.1
UART Transmit
P0.2
UART Receive
Not
Recommended
for
New
Designs
